Abstract: A video dot clock generator includes a phase-locked loop (PLL) which includes a voltage controlled oscillator, a frequency divider, a phase comparator and a loop filter. The voltage controlled oscillator (VCO) is programmable to provide multiple frequency ranges for a given range of control voltages applied to the oscillator. The programming affects both the frequency range and the gain of the VCO. The phase comparator includes circuitry which simulates a predetermined minimum phase error which, when compensated for, substantially eliminates jitter in the dot clock signal. The frequency divider used in the PLL and a similar frequency divided used to generate the reference signals for the phase comparator are programmable via an internal memory which also holds programmable control signals for the VCO. The memory, in turn, may be programmed by the user to achieve desired frequency and loop again characteristics for a given application.

Abstract: A novel high speed gallium arsenide depletion mode field effect transistor logic circuit is provided. One logic input is connected to the source electrode of the switching transistor and draws current when a low level input voltage is provided. Other logic inputs are connected to the gate electrode of the switching transistor and supplies current when a high or low level input voltage is provided. The novel logic output from the source electrode of the switching transistor is a complex OR function which may be employed for a logic family having fewer stages of logic than prior art gallium arsenide circuits.

Abstract: An improved high speed gallium arsenide (GaAs) to emitter coupled logic (ECL) voltage level converter is provided which consumes less power and also provides an improved speed-power product performance characteristic. The converter includes a three branch output circuit which emulates the operation of an ECL output driver. The emulator circuit causes faster switching by compensating for parasitic resistances and capacitance and is also provided with a gate discharge network which reduces switching time of the ECL output emulator.

Abstract: A gallium arsenide buffer amplifier for use in a very large scale integrated circuits is provided. The transistor device in the buffer amplifier has a uniform depth N+ source, gate and drain region and the N+ dopant concentration is made very high which effectively reduces the resistance of the transistor device and permits the area of the device to be reduced by more than one order of magnitude while maintaining high current and power levels.

Abstract: A high speed gallium arsenide (GaAs) integrated circuit is provided which converts GaAs input or source signals to voltage levels for directly driving emitter coupled logic (ECL) circuits. The high speed GaAs level converter comprises a level shifting network at the input, two stages of differential amplification and a novel source follower output stage.

Abstract: The present invention provides a high-speed low-power gallium arsenide basic logic circuit which is capable of being driven by either emitter coupled logic or gallium arsenide logic level signals to provide combinational logic gating such as OR-AND, OR-NAND, OR-AND-OR and OR-AND-NOR capable of driving directly either emitter coupled logic or gallium arsenide logic circuits. The combinational logic gating is basically accomplished by diode logic which performs other functions and which requires less area on an integrated circuit chip than active switching transistors.

Abstract: This invention provides a novel high-gain stabilized converter circuit which is adapted to convert emitter coupled logic (ECL) signals for use in gallium arsenide (Ga As) circuits. The novel converter is adapted to be made in gallium arsenide logic on the same chip as the logic circuitry which it is driving. The converter includes a novel differential amplifier having a level shifting network at the active input and a second level shifting network at the reference input to provide a stabilized high-gain circuit which is compensated for variations in temperature and process deviations.

Abstract: A CMOS timing device having a primary oscillatory reference source, a chain of series connected bistable divider stages whose data outputs are applied to a decoder/display by way of a multiplexing network. The multiplexing network is comprised of a plurality of multiplex sections, each section having a plurality of data transmission channels or paths. Each channel includes a plurality of MOS devices of a first type connected to a common bus. All channels driving the common bus share a single MOS device of a second type which provides a complementary function with respect to the first type to establish predetermined operating voltage levels for the data logic states carried by the common bus. The data on the common bus of each multiplex section is stored in a CMOS bistable latching type flip-flop whose regenerative feedback path is MOS device controlled.