Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Abstract: A network device includes card slots and Network Module slots that be reconfigured to hold cards and network modules having different form factors.

Abstract: A network device includes card slots and Network Module slots that be reconfigured to hold cards and network modules having different form factors.

Abstract: A router includes WIC and Network Module slots that be reconfigured to hold cards and network modules having different form factors. A motherboard/midplane arrangement provides for a field replaceable motherboard that can be replaced without removing the router from the rack.

Abstract: A cable device includes an integrated surge protection circuit. In the event that, communication signals conveyed by the cable include (potentially damaging) transient voltages, the surge protection circuit integrated in the cable suppresses the transient voltages at a distance from a corresponding electronic circuit to which the cable is attached. Consequently, potentially damaging voltage transients imparted on the communication signals are clamped before reaching potentially sensitive inputs of the electronic circuit.

Abstract: A router includes WIC and Network Module slots that be reconfigured to hold cards and network modules having different form factors. A motherboard/midplane arrangement provides for a field replaceable motherboard that can be replaced without removing the router from the rack.