Patents by Inventor Stephen A. Schlapp

Stephen A. Schlapp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Frame buffer memory with on-chip AIU and pixel cache
    Patent number: 6262748
    Abstract: A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: July 17, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, Stephen A. Schlapp, Michael G. Lavelle
  • Graphics system with multiported pixel buffers for accelerated pixel processing
    Patent number: 6195106
    Abstract: A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: February 27, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, Stephen A. Schlapp, Michael G. Lavelle
  • Interface controller for frame buffer random access memory devices
    Patent number: 5579473
    Abstract: A frame buffer memory device controller that schedules and dispatches operations to frame buffer memory devices is disclosed. The frame buffer memory device controller schedules and dispatches cache control operations to reduce timing overheads caused by cache prefetch operations, and operations to write back dirty cache lines and clear cache lines in the frame buffer memory devices. The frame buffer memory device controller also schedules and dispatches control operations to reduce timing overheads caused by video refresh operations from the frame buffer memory devices video output ports.
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: November 26, 1996
    Assignee: Sun Microsystems, Inc.
    Inventors: Stephen A. Schlapp, Michael F. Deering, Ewa M. Kubalska, Michael G. Lavelle
  • Flexible dram access in a frame buffer memory and system
    Patent number: 5544306
    Abstract: A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.
    Type: Grant
    Filed: May 3, 1994
    Date of Patent: August 6, 1996
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, Stephen A. Schlapp, Michael G. Lavelle