Patents by Inventor Stephen A. St. Onge
Stephen A. St. Onge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060154440Abstract: Methods of manufacturing a semiconductor structure are disclosed including a deep trench isolation in which a channel stop is formed in the form of an embedded impurity region in the substrate prior to the deep trench etch and formation of transistor devices (FEOL processing) on the substrate. In this fashion, the FEOL processing thermal cycles can activate the impurity region. The deep trench isolations are then formed after FEOL processing. The method achieves the reduced cost of forming deep trench isolations after FEOL processing, and allows the practice of sharing of a collector level between devices to continue. The invention also includes the semiconductor structure so formed.Type: ApplicationFiled: January 13, 2005Publication date: July 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis Lanzerotti, Stephen St. Onge
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Patent number: 7002221Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.Type: GrantFiled: August 29, 2003Date of Patent: February 21, 2006Assignee: International Business Machines CorporationInventors: Marwan H. Khater, James S. Dunn, David L. Harame, Alvin J. Joseph, Qizhi Liu, Francois Pagette, Stephen A. St. Onge, Andreas D. Stricker
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Patent number: 6998699Abstract: A bipolar transistor having a base contact surrounded by an emitter contact. A plurality of wires extending from the base contact and the emitter contact of the bipolar transistor, wherein the wires of the base contact are stacked higher than the wires of the emitter contact. A device comprising a plurality of these bipolar transistors, wherein at least one side of each emitter contact abuts each adjacent transistor. Increasing the wiring stack of each row of transistors in the device as the distance between the row and the current input increases.Type: GrantFiled: August 21, 2003Date of Patent: February 14, 2006Assignee: International Business Machines CorporationInventors: Michael D. Hulvey, Stephen A. St. Onge
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Publication number: 20050189618Abstract: A bipolar transistor having a base contact surrounded by an emitter contact. A plurality of wires extending from the base contact and the emitter contact of the bipolar transistor, wherein the wires of the base contact are stacked higher than the wires of the emitter contact. A device comprising a plurality of these bipolar transistors, wherein at least one side of each emitter contact abuts each adjacent transistor. Increasing the wiring stack of each row of transistors in the device as the distance between the row and the current input increases.Type: ApplicationFiled: August 21, 2003Publication date: September 1, 2005Inventors: Michael Hulvey, Stephen St. Onge
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Patent number: 6900519Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.Type: GrantFiled: June 10, 2004Date of Patent: May 31, 2005Assignee: International Business Machines CorporationInventors: Marc W. Cantell, James S. Dunn, David L. Harame, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
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Patent number: 6869854Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.Type: GrantFiled: July 18, 2002Date of Patent: March 22, 2005Assignee: International Business Machines CorporationInventors: Marc W. Cantell, James S. Dunn, David L. Harame, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
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Publication number: 20050048735Abstract: A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.Type: ApplicationFiled: August 29, 2003Publication date: March 3, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marwan Khater, James Dunn, David Harame, Alvin Joseph, Qizhi Liu, Francois Pagette, Stephen St. Onge, Andreas Stricker
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Publication number: 20040222495Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.Type: ApplicationFiled: June 10, 2004Publication date: November 11, 2004Inventors: Marc W. Cantell, James S. Dunn, David L. Harama, Robb A. Johnson, Louis D. Lametotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
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Publication number: 20040014271Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device.Type: ApplicationFiled: July 18, 2002Publication date: January 22, 2004Applicant: International Business Machines CorporationInventors: Marc W. Cantell, James S. Dunn, David L. Harame, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge, Brian L. Tessier, Ryan W. Wuthrich
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Patent number: 6657280Abstract: A bipolar transistor having a base contact surrounded by an emitter contact. A plurality of wires extending from the base contact and the emitter contact of the bipolar transistor, wherein the wires of the base contact are stacked higher than the wires of the emitter contact. A device comprising a plurality of these bipolar transistors, wherein at least one side of each emitter contact abuts each adjacent transistor. Increasing the wiring stack of each row of transistors in the device as the distance between the row and the current input increases.Type: GrantFiled: November 13, 2000Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Michael D. Hulvey, Stephen A. St. Onge
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Patent number: 6600199Abstract: The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.Type: GrantFiled: December 29, 2000Date of Patent: July 29, 2003Assignee: International Business Machines CorporationInventors: Steven H. Voldman, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge
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Patent number: 6597050Abstract: A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.Type: GrantFiled: May 19, 2000Date of Patent: July 22, 2003Assignee: International Business Machines CorporationInventors: James Stuart Dunn, Peter Brian Gray, Kenneth Knetch Kieft, III, Nicholas Theodore Schmidt, Stephen St. onge
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Patent number: 6476483Abstract: In an electronic device with an active region on top of and isolated from an substrate, a first material region is defined on top of and/or adjacent to and electrically isolated from the active region and a second material region is attached to a surface of the first material region to form an interface defining a Peltier cooling junction therebetween. A current source connected in series to the first and the second material regions produces a cooling effect at the Peltier cooling junction.Type: GrantFiled: October 20, 1999Date of Patent: November 5, 2002Assignee: International Business Machines CorporationInventors: Eric Adler, James S. Dunn, Kent E. Morrett, Edward J. Nowak, Stephen A. St. Onge
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Patent number: 6452251Abstract: A capacitor (60 and 126) fabricated on a semiconductor chip which has a strap contact (41A, 119A) which interconnects the bottom plate (41B, 111A) of the capacitor into the chip circuitry. In one version, an extension of the material making up the bottom plate of the capacitor forms the strap contact. In another version, the capacitor (185) includes a folding of the bottom plate, dielectric layer and top plate to utilize available space and thus increase its capacitance. Several manufacturing methods allow for integration of fabrication of the various versions of the capacitor into a standard dual or single damascene manufacturing process, including a copper damascene process.Type: GrantFiled: March 31, 2000Date of Patent: September 17, 2002Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Robert M. Geffken, Anthony K. Stamper, Stephen A. St. Onge
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Patent number: 6448124Abstract: A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.Type: GrantFiled: November 12, 1999Date of Patent: September 10, 2002Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, James S. Dunn, Peter J. Geiss, Peter B. Gray, David L. Harame, Kathryn T. Schonenberg, Stephen A. St. Onge, Seshadri Subbanna
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Publication number: 20020084506Abstract: The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. Additionally, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.Type: ApplicationFiled: December 29, 2000Publication date: July 4, 2002Applicant: International Business Machines CorporationInventors: Steven H. Voldman, Robb A. Johnson, Louis D. Lanzerotti, Stephen A. St. Onge
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Publication number: 20020076874Abstract: A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.Type: ApplicationFiled: November 12, 1999Publication date: June 20, 2002Inventors: DOUGLAS D. COOLBAUGH, JAMES S. DUNN, PETER J. GEISS, PETER B. GRAY, DAVID L. HARAME, KATHRYN T. SCHONENBERG, STEPHEN A. ST. ONGE, SESHADRI SUBBANNA
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Patent number: 6329690Abstract: A semiconductor structure may include a silicon substrate, a first active device formed in a first region of the silicon substrate, a second active device formed in a second region of the silicon substrate, a first heating device connected thermally to the first active device and a second heating device connected thermally to the second active device. A first temperature sensing device detects a temperature of the first region, a second temperature sensing device detects a temperature of the second region and a circuit activates one of the first heating device and the second heating device in response to a sensed difference in temperature from the first and second temperature sensing devices.Type: GrantFiled: October 22, 1999Date of Patent: December 11, 2001Assignee: International Business Machines CorporationInventors: Kent E. Morrett, Edward J. Nowak, Stephen A. St. Onge, Josef S. Watts
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Patent number: 6258695Abstract: A method of reducing the formation of silicon crystal defects due to extrinsic stresses in an integrated circuit chip. The source of such extrinsic stresses may be filling trenches with polycrystalline silicon or oxide, silicides, forming silicon nitride spacers or liners, or during oxide birds-beak formation, or at numerous other processing points. At an appropriate point, as each sensitive feature is defined or formed, carbon co-implanted into the silicon wafer at or near the feature.Type: GrantFiled: February 4, 1999Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: James Dunn, Peter Geiss, Stephen St. Onge
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Patent number: 6121122Abstract: A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.Type: GrantFiled: May 17, 1999Date of Patent: September 19, 2000Assignee: International Business Machines CorporationInventors: James Stuart Dunn, Peter Brian Gray, Kenneth Knetch Kieft, III, Nicholas Theodore Schmidt, Stephen St. onge