Patents by Inventor Stephen A. Weis
Stephen A. Weis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240131303Abstract: An endovascular management and tracking system comprises a track and at least one shuttle to which at least one elongate medical device can be respectively affixed. Each of the shuttle(s) is configured for being mechanically coupled to the track. Each of the shuttle(s) comprises a sled configured for riding on the track, an axial drive mechanism carried by the sled and configured for being actuated to axially translate the respective shuttle along the track, and a first actuator carried by the sled and configured for actuating the axial drive mechanism.Type: ApplicationFiled: December 29, 2023Publication date: April 25, 2024Applicants: STRYKER CORPORATION, STRYKER EUROPEAN OPERATIONS LIMITEDInventors: Stephen Porter, Brady Esch, Halil Karabey, Han-Wei Wang, Anirudh Anupam Chaturvedi
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Patent number: 11944007Abstract: There is disclosed squaraine compounds of formula I: wherein each of Y1 and Y2 is independently chosen from an optionally substituted amino group and an optionally substituted aryl group. Also described are organic optoelectronic devices comprising a Donor-Acceptor heterojunction that is formed from one or more of the squaraine compounds. A method of making the disclosed device, which may include one or more sublimation step for depositing said squaraine compound, is also disclosed.Type: GrantFiled: June 24, 2019Date of Patent: March 26, 2024Assignees: The Regents of the University of Michigan, University of Southern CaliforniaInventors: Mark E. Thompson, Stephen R. Forrest, Guodan Wei, Siyi Wang, Lincoln Hall, Viacheslav V. Diev, Xin Xiao
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Patent number: 11933786Abstract: Antibodies that selectively bind to glycosylated PD-1 relative to unglycosylated PD-1 are provided. In some aspects, PD-1 polypeptides comprising glycosylated amino acid positions are also provided. Methods for making and using such antibodies and polypeptides (e.g., for the treatment of cancer) are also provided.Type: GrantFiled: November 13, 2020Date of Patent: March 19, 2024Assignees: STCUBE, INC., BOARD OF REGENTS, THE UNIVERSITY OF TEXASInventors: Stephen S. Yoo, Ezra M. Chung, Yong-Soo Kim, Mien-Chie Hung, Chia-Wei Li, Seung-Oe Lim
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Publication number: 20240087583Abstract: An encoder operable to filter audio signals into a plurality of frequency band components, generate quantized digital components for each band, identify a potential for pre-echo events within the generated quantized digital components, generate an approximate signal by decoding the quantized digital components using inverse pulse code modulation, generate an error signal by comparing the approximate signal with the sampled audio signal, and process the error signal and quantized digital components. The encoder operable to process the error signal by processing delayed audio signals and Q band values, determining the potential for pre-echo events from the Q band values, and determining scale factors and MDCT block sizes for the potential for pre-echo events.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: IMMERSION NETWORKS, INC.Inventors: James David Johnston, Stephen Daniel White, King Wei Hor, Barry M. Genova
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Patent number: 10049048Abstract: A processor cache is logically partitioned into a main partition, located in the cache itself, and an enclave partition, located within an enclave, that is, a hardware-enforced protected region of an address space of a memory. This extends the secure address space usable by and for an application such as a software cryptoprocessor that is to execute only in secure regions of cache or memory.Type: GrantFiled: October 1, 2014Date of Patent: August 14, 2018Assignee: Facebook, Inc.Inventors: Oded Horovitz, Stephen A. Weis, Sahil Rihan, Carl A. Waldspurger
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Publication number: 20180217941Abstract: A processor cache is logically partitioned into a main partition, located in the cache itself, and an enclave partition, located within an enclave, that is, a hardware-enforced protected region of an address space of a memory. This extends the secure address space usable by and for an application such as a software cryptoprocessor that is to execute only in secure regions of cache or memory.Type: ApplicationFiled: October 1, 2014Publication date: August 2, 2018Inventors: Oded HOROVITZ, Stephen A. WEIS, Sahil RIHAN, Carl A. WALDSPURGER
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Patent number: 10037282Abstract: A system and method of operation exploit the limited associativity of a single cache set to force observable cache evictions and discover conflicts. Loads are issued to input memory addresses, one at a time, until a cache eviction is detected. After observing a cache eviction on a load from an address, that address is added to a data structure representing the current conflict set. The cache is then flushed, and loads are issued to all addresses in the current conflict set, so that all known conflicting addresses are accessed first, ensuring that the next cache miss will occur on a different conflicting address. The process is repeated, issuing loads from all input memory addresses, incrementally finding conflicting addresses, one by one. Memory addresses that conflict in the cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict.Type: GrantFiled: September 23, 2016Date of Patent: July 31, 2018Assignee: Facebook, Inc.Inventors: Carl A. Waldspurger, Oded Horovitz, Stephen A. Weis, Sahil Rihan
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Patent number: 9983894Abstract: An application such as a virtual machine are executed securely using a software-based, full-system emulator within a hardware-protected enclave, such as an SGX enclave. The emulator may thereby be secure even against a malicious underlying host operating system. In some cases, paging is used to allow even a large application may run within a small enclave using paging. Where the application itself uses enclaves, these guest enclaves may themselves be emulated within an emulator enclave such that the guest enclave(s) are nested as sibling enclaves by the emulator.Type: GrantFiled: September 25, 2014Date of Patent: May 29, 2018Assignee: Facebook, Inc.Inventors: Oded Horovitz, Stephen A. Weis, Sahil Rihan, Carl A. Waldspurger
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Patent number: 9747450Abstract: An attestation system for asserting and verifying assertions of a known-good state of a computer system is provided. The attestation system allows a challenger and a prover to conduct an attestation so that the challenger can verify an assertion of the prover. To conduct the attestation, the prover sends, as an assertion of its state, a combined measurement of resources along with a constituent measurement of each resource to the challenger. The challenger verifies the assertion by verifying that the asserted constituent measurements represent known-good measurements and verifying that the asserted combined measurement can be generated from the asserted constituent measurements. To verify the asserted constituent measurements, the challenger determines whether each asserted constituent measurement for a resource is a known-good measurement for that resource.Type: GrantFiled: February 10, 2015Date of Patent: August 29, 2017Assignee: Facebook, Inc.Inventors: Oded Horovitz, Sahil Rihan, Stephen A. Weis, Daniel Arai
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Patent number: 9734092Abstract: Methods and systems for securing sensitive data from security risks associated with direct memory access (“DMA”) by input/output (“I/O”) devices are provided. An enhanced software cryptoprocessor system secures sensitive data using various techniques, including (1) protecting sensitive data by preventing DMA by an I/O device to the portion of the cache that stores the sensitive data, (2) protecting device data by preventing cross-device access to device data using DMA isolation, and (3) protecting the cache by preventing the pessimistic eviction of cache lines on DMA writes to main memory.Type: GrantFiled: March 19, 2015Date of Patent: August 15, 2017Assignee: Facebook, Inc.Inventors: Oded Horovitz, Sahil Rihan, Stephen A. Weis, Carl A. Waldspurger
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Publication number: 20170206167Abstract: A system and method of operation exploit the limited associativity of a single cache set to force observable cache evictions and discover conflicts. Loads are issued to input memory addresses, one at a time, until a cache eviction is detected. After observing a cache eviction on a load from an address, that address is added to a data structure representing the current conflict set. The cache is then flushed, and loads are issued to all addresses in the current conflict set, so that all known conflicting addresses are accessed first, ensuring that the next cache miss will occur on a different conflicting address. The process is repeated, issuing loads from all input memory addresses, incrementally finding conflicting addresses, one by one. Memory addresses that conflict in the cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict.Type: ApplicationFiled: September 23, 2016Publication date: July 20, 2017Inventors: Carl A. Waldspurger, Oded Horovitz, Stephen A. Weis, Sahil Rihan
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Patent number: 9639482Abstract: Security of information—both code and data—stored in a computer's system memory is provided by an agent loaded into and at run time resident in a CPU cache. Memory writes from the CPU are encrypted by the agent before writing and reads into the CPU are decrypted by the agent before they reach the CPU. The cache-resident agent also optionally validates the encrypted information stored in the system memory. Support for I/O devices and cache protection from unsafe DMA of the cache by devices is also provided.Type: GrantFiled: August 6, 2015Date of Patent: May 2, 2017Assignee: Facebook, Inc.Inventors: Oded Horovitz, Stephen A. Weis, Carl A. Waldspurger, Sahil Rihan
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Patent number: 9477603Abstract: A system and method of operation exploit the limited associativity of a single cache set to force observable cache evictions and discover conflicts. Loads are issued to input memory addresses, one at a time, until a cache eviction is detected. After observing a cache eviction on a load from an address, that address is added to a data structure representing the current conflict set. The cache is then flushed, and loads are issued to all addresses in the current conflict set, so that all known conflicting addresses are accessed first, ensuring that the next cache miss will occur on a different conflicting address. The process is repeated, issuing loads from all input memory addresses, incrementally finding conflicting addresses, one by one. Memory addresses that conflict in the cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict.Type: GrantFiled: September 5, 2014Date of Patent: October 25, 2016Assignee: FACEBOOK, INC.Inventors: Carl A. Waldspurger, Oded Horovitz, Stephen A. Weis, Sahil Rihan
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Publication number: 20160224475Abstract: Security of information—both code and data—stored in a computer's system memory is provided by an agent loaded into and at run time resident in a CPU cache. Memory writes from the CPU are encrypted by the agent before writing and reads into the CPU are decrypted by the agent before they reach the CPU. The cache-resident agent also optionally validates the encrypted information stored in the system memory. Support for I/O devices and cache protection from unsafe DMA of the cache by devices is also provided.Type: ApplicationFiled: August 6, 2015Publication date: August 4, 2016Inventors: Oded Horovitz, Stephen A. Weis, Carl A. Waldspurger, Sahil Rihan
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Patent number: 9164924Abstract: Security of information—both code and data—stored in a computer's system memory is provided by an agent loaded into and at run time resident in a CPU cache. Memory writes from the CPU are encrypted by the agent before writing and reads into the CPU are decrypted by the agent before they reach the CPU. The cache-resident agent also optionally validates the encrypted information stored in the system memory. Support for I/O devices and cache protection from unsafe DMA of the cache by devices is also provided.Type: GrantFiled: September 13, 2012Date of Patent: October 20, 2015Assignee: FACEBOOK, INC.Inventors: Oded Horovitz, Stephen A. Weis, Carl A. Waldspurger, Sahil Rihan
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Publication number: 20150269091Abstract: Methods and systems for securing sensitive data from security risks associated with direct memory access (“DMA”) by input/output (“I/O”) devices are provided. An enhanced software cryptoprocessor system secures sensitive data using various techniques, including (1) protecting sensitive data by preventing DMA by an I/O device to the portion of the cache that stores the sensitive data, (2) protecting device data by preventing cross-device access to device data using DMA isolation, and (3) protecting the cache by preventing the pessimistic eviction of cache lines on DMA writes to main memory.Type: ApplicationFiled: March 19, 2015Publication date: September 24, 2015Inventors: Oded Horovitz, Sahil Rihan, Stephen A. Weis, Carl A. Waldspurger
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Publication number: 20150227744Abstract: An attestation system for asserting and verifying assertions of a known-good state of a computer system is provided. The attestation system allows a challenger and a prover to conduct an attestation so that the challenger can verify an assertion of the prover. To conduct the attestation, the prover sends, as an assertion of its state, a combined measurement of resources along with a constituent measurement of each resource to the challenger. The challenger verifies the assertion by verifying that the asserted constituent measurements represent known-good measurements and verifying that the asserted combined measurement can be generated from the asserted constituent measurements. To verify the asserted constituent measurements, the challenger determines whether each asserted constituent measurement for a resource is a known-good measurement for that resource.Type: ApplicationFiled: February 10, 2015Publication date: August 13, 2015Inventors: Oded Horovitz, Sahil Rihan, Stephen A. Weis, Daniel Arai
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Publication number: 20150089502Abstract: An application such as a virtual machine are executed securely using a software-based, full-system emulator within a hardware-protected enclave, such as an SGX enclave. The emulator may thereby be secure even against a malicious underlying host operating system. In some cases, paging is used to allow even a large application may run within a small enclave using paging. Where the application itself uses enclaves, these guest enclaves may themselves be emulated within an emulator enclave such that the guest enclave(s) are nested as sibling enclaves by the emulator.Type: ApplicationFiled: September 25, 2014Publication date: March 26, 2015Applicant: PrivateCore, Inc.Inventors: Oded HOROVITZ, Stephen A. WEIS, Sahil RIHAN, Carl A. WALDSPURGER
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Publication number: 20150067265Abstract: A system and method of operation exploit the limited associativity of a single cache set to force observable cache evictions and discover conflicts. Loads are issued to input memory addresses, one at a time, until a cache eviction is detected. After observing a cache eviction on a load from an address, that address is added to a data structure representing the current conflict set. The cache is then flushed, and loads are issued to all addresses in the current conflict set, so that all known conflicting addresses are accessed first, ensuring that the next cache miss will occur on a different conflicting address. The process is repeated, issuing loads from all input memory addresses, incrementally finding conflicting addresses, one by one. Memory addresses that conflict in the cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict.Type: ApplicationFiled: September 5, 2014Publication date: March 5, 2015Applicant: PRIVATECORE, INC.Inventors: Carl A. WALDSPURGER, Oded HOROVITZ, Stephen A. WEIS, Sahil RIHAN
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Patent number: 8930001Abstract: A method of model identification for a process with unknown initial conditions in an industrial plant, the method comprising collecting a set of manipulated variables and corresponding set of process variables from the process; obtaining a plurality of manipulated variables from the collected set of manipulated variables; for each of the plurality of manipulated variables, obtaining optimal model parameters of a model transfer function and computing a model fitting index for optimized simulated process variables generated by the model transfer function using the optimal model parameters; identifying a best model fitting index among the model fitting indices computed; selecting a manipulated variable associated with the best model fitting index as an initial steady state condition for the model transfer function; and selecting the optimal model parameters corresponding with the best model fitting index as the best model parameters of the model transfer function to tune the controller.Type: GrantFiled: September 19, 2011Date of Patent: January 6, 2015Assignee: Yokogawa Electric CorporationInventors: Shengjing Mu, Stephen Wei Hong Weng, Joseph Ching Hua Lee