Patents by Inventor Stephen Alan Fanelli

Stephen Alan Fanelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Porous silicon post processing
    Patent number: 10134837
    Abstract: A semiconductor on insulator (SOI) device may include a semiconductor handle substrate. The semiconductor hand may include a porous semiconductor layer, and an etch stop layer proximate the porous semiconductor layer. The SOI may also include an insulator layer on the etch stop layer. The SOI may further include a device semiconductor layer on the insulator layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Stephen Alan Fanelli, Richard Hammond
  • POROUS SILICON DICING
    Publication number: 20180301419
    Abstract: A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.
    Type: Application
    Filed: July 24, 2017
    Publication date: October 18, 2018
    Inventors: Stephen Alan FANELLI, Richard HAMMOND
  • POROUS SEMICONDUCTOR HANDLE SUBSTRATE
    Publication number: 20180277632
    Abstract: An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.
    Type: Application
    Filed: August 4, 2017
    Publication date: September 27, 2018
    Inventors: Stephen Alan FANELLI, Richard HAMMOND
  • WRAP-AROUND GATE STRUCTURES AND METHODS OF FORMING WRAP-AROUND GATE STRUCTURES
    Publication number: 20180233600
    Abstract: A semiconductor device includes a channel structure that includes a first oxide layer, a second oxide layer, and a channel region between the first oxide layer and the second oxide layer. The semiconductor device includes a first gate structure proximate to at least three sides of the channel structure. The semiconductor device includes a second gate structure proximate to at least a fourth side of the channel structure.
    Type: Application
    Filed: January 24, 2018
    Publication date: August 16, 2018
    Inventors: Ravi Pramod Kumar Vedula, Stephen Alan Fanelli, Farid Azzazy
  • Methods of forming a device having semiconductor devices on two sides of a buried dielectric layer
    Patent number: 9837302
    Abstract: A method includes performing an etching process from a second side of a buried dielectric layer to expose an etch stop layer, where the second side of the buried dielectric layer is opposite a first side of the buried dielectric layer, and where a first semiconductor device is positioned on the first side of the buried dielectric layer. The method further includes forming a second semiconductor device on the second side of the buried dielectric layer.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: December 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Stephen Alan Fanelli