Abstract: State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 12 is controlled by a first clock signal nclk and a second clock signal bclk. The tristate inverter circuitry 2 is controlled by a third clock signal nfclk and a fourth clock signal flck. The clock generating circuitry holds the third and fourth clock signals at fixed values which tristate the tristate inverter circuitry 2 when in scan mode. This moves scan control logic out of the function path comprising the tristate inverter circuitry into the clock control circuitry.

Abstract: The application discloses storage circuitry with a pulse generator used to control switches on two inputs to the storage circuitry thereby connecting either operational data or diagnostic data to the storage circuitry. Thus, the pulse generator selects the data paths by outputting pulses to a diagnostic output or to a functional output, and these pulses controlling the switches on the two inputs to the storage circuitry.

Abstract: The application discloses state storage circuitry comprising: an operational data input for receiving input data, a diagnostic data input for receiving diagnostic data and a diagnostic select signal input; a storage element for storing a value indicative of data received from one of said operational data input and said diagnostic data input; an output for outputting said value stored in said storage element; a pulse generator for generating pulses in response to a clock signal, said pulse generator comprising a diagnostic output and a functional output and being responsive to receipt of a diagnostic enable signal at said diagnostic select signal input to output said generated pulses at said diagnostic output and being responsive to receipt of a diagnostic disable signal at said diagnostic select signal input to output said generated pulses at said functional output; an operational path switch for receiving said pulses from said functional output and being responsive to receipt of each of said pulses to provid

Abstract: State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 12 is controlled by a first clock signal nclk and a second clock signal bclk. The tristate inverter circuitry 2 is controlled by a third clock signal nfclk and a fourth clock signal flck. The clock generating circuitry holds the third and fourth clock signals at fixed values which tristate the tristate inverter circuitry 2 when in scan mode. This moves scan control logic out of the function path comprising the tristate inverter circuitry into the clock control circuitry.