Abstract: According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the fabrication process, the body of a transistor is formed from a pillar of single crystal silicon. The silicon pillar is formed over a butted junction of N+ and P+ diffusions. This fabrication process results in a pillar structure which has an n+ diffusion contacting a portion of the base of the transistor body and a P+ diffusion contacting the remainder of the base of the transistor body. The proportion of N+ and P+ area at the base of the silicon pillar depends on the overlay of the opening to the butted junction. Gate oxide is grown over the entire pillar and a polysilicon gate material is then deposited and etched to form the transistor gate. Metal contact studs are formed, preferably via deposition. After fabrication, the entire surface of the device can be planarized by using any standard Chemical Mechanical Planarization (CMP) process.

Abstract: According to the present invention, a method for fabricating vertical circuit devices which include a body contact is disclosed. During the fabrication process, the body of a transistor is formed from a pillar of single crystal silicon. The silicon pillar is formed over a butted junction of N+ and P+ diffusions. This fabrication process results in a pillar structure which has an n+ diffusion contacting a portion of the base of the transistor body and a P+ diffusion contacting the remainder of the base of the transistor body. The proportion of N+ and P+ area at the base of the silicon pillar depends on the overlay of the opening to the butted junction. Gate oxide is grown over the entire pillar and a polysilicon gate material is then deposited and etched to form the transistor gate. Metal contact studs are formed, preferably via deposition. After fabrication, the entire surface of the device can be planarized by using any standard Chemical Mechanical Planarization (CMP) process.