Abstract: An integrated circuit allows a user or system designer to program the length of a transaction cycle by programming the lengths of the setup time period, the command time period and the recovery time period, individually. An eight-bit register is used to store a two-bit prescaler value and a six-bit count value for each of the setup, command and recovery time periods. The value represented by the prescaler is then multiplied by the count value and the resulting value is input to a timer which counts down from the resulting value, signalling to a state machine when it has reached zero. A four-state state machine sends the command to begin each transaction cycle and each setup, command and recovery time period within each transaction cycle. The state machine is notified by the timer when the time period has elapsed for each of the three states so that it can send the signal to begin the next state.

Abstract: A selective low power clocking apparatus and method is used to reduce power consumption by an electronic system or integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits or functional blocks. Each sub-circuit or functional block is configured to operate under control of a clock signal and further includes an apparatus for holding or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, the clock signal to that sub-circuit is disabled. The arbiter circuit continuously monitors the system bus. Upon detecting that the external system needs to transmit or receive signals from the electronic system or integrated circuit, the arbiter re-enables the clock signal to the sub-circuits which are required for the transmission or reception.