Abstract: A memory configuration for use in a computer system includes a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states. A data memory having a plurality of word lines of predetermined length, is also included in each of the address decoders and is activatable to select one of the plurality of word lines. The address decoders receive an input address having a predetermined number of bits and compare the identifier of an address decoder with the input address wherein the memory further activates an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier.

Abstract: A neural network component includes a plurality of inputs, at least one processing element, at least one output, and a digital memory storing values at addresses respectively corresponding to the at least one processing element, wherein the at least one processing element is arranged to receive a value from the digital memory in response to an input signal, and is instructed to execute one of a plurality of operations by the value that is received from the digital memory.

Abstract: A pulse circuit contains an input stage configured to receive input pulses on input nodes using push-pull elements, wherein a given push-pull element is configured to receive an input pulse on a given input node and to provide a corresponding internal signal. The pulse circuit further contains a feedback loop that includes a logic element coupled between outputs from the push-pull elements and reset nodes of the push-pull elements. This logic element is configured to provide one or more outputs from the pulse circuit and to reset the internal signals from the push-pull elements via the feedback loop.