Abstract: Apparatus and methods are provided for managing SAS zone group permission tables using associated version identifiers. Zone group permission tables of a SAS domain may have associated version identifiers, indicating a version of the zone group permission table. The version identifier may be used to determine whether the zone group permission table is the same as the current version for the SAS domain without comparing the contents of the zone group permission table with the contents of the current version. The version identifier may also be used for determining which of a plurality of zone group permission tables of the SAS domain is the current version if two or more SAS zoning expanders are storing different zone group permission tables.

Abstract: At least one first numbered phy of a first SAS expander is grouped with at least one second numbered phy of a second SAS expander physically separate from the first SAS expander into at least one common SAS wide port. An identical SAS address is assigned to the first SAS expander and the second SAS expander for operating the first SAS expander and the second SAS expander to behave and respond as a single, cohesive SAS expander. The first SAS expander is directly connected to the second SAS expander for inter-expander communications.

Abstract: A failed link is detected between a first SAS expander and a device. A data transfer of the first SAS expander connected to the device via the failed link is re-routed to a second SAS expander connected to the device via a functional link. The first SAS expander is connected to the SAS expander via the phys of the first SAS expander and the phys of the second SAS expander for inter-expander communications.

Abstract: The optimal lanes of at least one SAS wide port for the data connection are discovered. The allowable lanes for the data connection within the SAS wide ports of each level of the SAS domain are specified. The specified allowable lanes for the data connection are checked. The data connection is created on the specified allowable lanes.

Abstract: An input port is assigned to a SAS expander device. An output port is assigned to the SAS expander device. The output port and the input port are defined to be paired with each other as a primary subtractive port. Only a SAS initiator address is programmed in the route table of the SAS expander. An OPEN command is sent out the output port upon receiving the OPEN command into the input port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device. An OPEN command is sent out the input port upon receiving the OPEN command into the output port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device.

Abstract: Defibrillator assemblies and methods to wirelessly transfer energy from an external source to a battery or other rechargeable power source within the defibrillator assembly. The transfer of energy may be through a non-contact interface on a defibrillator cradle or a docking station that mounts the defibrillator. The rate of energy transfer may be equal to the energy drain caused by self-discharge and automated self-testing. Accordingly, since the rate of energy transfer is lower than that required to run the defibrillator system continuously, several wireless methods of energy transfer may be used. In addition, the defibrillator assembly may communicate diagnostic and non-diagnostic data to the external source.

Abstract: A memory management unit (MMU) for a device controller that provides enhanced functionality while maintaining a small physical size or footprint, such that the die size required to manufacture the memory management unit circuitry within the device controller integrated circuit device remains small notwithstanding such enhanced functionality. This compact/tiny MMU provides virtual memory addressing and memory error detection functionality while maintaining a small physical die size. The small physical die size with enhanced functionality is obtained by improvements in translating virtual to physical addressing without use of extensive translation tables, which themselves would otherwise consume memory and associated die real estate. In addition, the MMU allows a firmware image containing code and data segments to be run-time swapped between internal shared context RAM and external memory.

Abstract: Defibrillator assemblies and methods to wirelessly transfer energy from an external source to a battery or other rechargeable power source within the defibrillator assembly. The transfer of energy may be through a non-contact interface on a defibrillator cradle or a docking station that mounts the defibrillator. The rate of energy transfer may be equal to the energy drain caused by self-discharge and automated self-testing. Accordingly, since the rate of energy transfer is lower than that required to run the defibrillator system continuously, several wireless methods of energy transfer may be used. In addition, the defibrillator assembly may communicate diagnostic and non-diagnostic data to the external source.

Abstract: Methods and systems for generating storage related load factor information for load balancing of multiple virtual machines operable in a cluster of multiple physical processors (such as a blade center). Load factor information is generated within a storage system relating to operation of the storage system as a whole and relating to each of multiple storage controllers in the storage system. The information so generated in the storage system is communicated to a load balancing element associated with the multiple virtual machines. The load balancing element then utilizes the storage related load factor information, optionally in combination with other load factor information, to distribute or redistribute the operation of the multiple virtual machines over the plurality of physical processors.

Abstract: Methods and systems for generating storage related load factor information for load balancing of multiple virtual machines operable in a cluster of multiple physical processors (such as a blade center). Load factor information is generated within a storage system relating to operation of the storage system as a whole and relating to each of multiple storage controllers in the storage system. The information so generated in the storage system is communicated to a load balancing element associated with the multiple virtual machines. The load balancing element then utilizes the storage related load factor information, optionally in combination with other load factor information, to distribute or redistribute the operation of the multiple virtual machines over the plurality of physical processors.

Abstract: Apparatus and methods are provided for managing SAS zone group permission tables using associated version identifiers. Zone group permission tables of a SAS domain may have associated version identifiers, indicating a version of the zone group permission table. The version identifier may be used to determine whether the zone group permission table is the same as the current version for the SAS domain without comparing the contents of the zone group permission table with the contents of the current version. The version identifier may also be used for determining which of a plurality of zone group permission tables of the SAS domain is the current version if two or more SAS zoning expanders are storing different zone group permission tables.

Abstract: A code efficient transfer method in response to a single host I/O request generates a single scatter gather list. The disk array controller transforms the single host I/O request into multiple physical I/O requests. Each of these multiple physical I/O requests uses the single scatter gather list to perform the data transfer operation. Each physical I/O request corresponds to the data transfer of one data stripe. The data stripe is an initial or header stripe of about 0.5K or a stripe of at least 64K.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a request count in response to a request head pointer and a request tail pointer. The second circuit may be configured to generate a completion count in response a completion head pointer and a completion tail pointer. The third circuit may be configured to prioritize an interrupt in response to the request and completion counts.

Abstract: The power source in a portable defibrillator includes a replaceable first power pack and a rechargeable second power pack. The first power pack charges the second power pack. The second power pack supplies most of the energy needed to administer a defibrillation shock. The first power pack may include one or more lithium thionyl chloride batteries. The second power pack may include one or more lithium ion batteries and/or ultracapacitors.

Abstract: An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO adapter. The firmware on the IO adapter may have a global variable that stores counters for PCI function registers. Each counter tracks the number of outstanding IOs of a corresponding PCI function register. The counter is incremented whenever a new IO is received and is decremented upon posting the completed message back to the OS. A timer interrupt is generated periodically so that an ISR may be periodically performed. In the ISR, the maximum value stored of each counter seen since last timer interrupt is analyzed. When the maximum value stored is greater than a predetermined threshold value, the interrupt coalescing is enabled.

Abstract: The present invention provides an apparatus and a method for embedding information from a first configuration data set having data structures into an embedded processing system, wherein embedding the information maintains user-defined variables. Embedding information includes comparing a first identifier from the first configuration data set with a second identifier from a second configuration data set having data structures to determine if the first identifier differs from the second identifier. In response to a determination of the first identifier differing from the second identifier, a decision is made to merge the first configuration data set with the second configuration data set to form a merged configuration data set. Afterwards, the merged configuration data set is written to the embedded processing system, wherein the merged configuration data set includes maintained user-defined variables.

Abstract: A mechanism is provided for controlling the heat output of a controller by monitoring the temperature of the controller using an embedded heat sensor. The IO processor monitors the temperature and controls the rate of the IO flow to control the temperature. The IO processor accomplishes this by checking the current temperature every time it gets a timer interrupt. If the temperature becomes too high, the IO processor may slow down the processor speeds in the controller. The IO processor may also slow down the throughput by inserting a delay between each IO request processed. Furthermore, the IO processor may slow down the rate at which data is passed onto the bus. Still further, the IO processor may insert a delay between batches of IO requests. By slowing down the IO flow, the IO processor decreases the overall power consumption and, thus, controls the heat output.

Abstract: Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operational programmed instructions for the intelligent host adapter device are stored in the nonvolatile memory of the system motherboard along with the standard BIOS code of the system. The intelligent host adapter device operational programmed instructions are then downloaded by the BIOS code into the host adapter's volatile local program memory to initialize operation of the intelligent host adapter device. Further, device driver code operable in the operating system on the motherboard will upload the previously downloaded programmed instructions from the intelligent host adapter so that the programmed instructions may be reloaded to the host adapter in response to reset conditions, power management events, and other conditions.

Abstract: An input/output controller that allows independent and configurable reduction of clock speeds to its embedded processors when they are not in use to save average power consumption. The processor clock speeds are restored when new input/output requests are received.

Abstract: This invention provides polymer filaments having a multilobal cross-section. The cross-section can have a filament factor of about 2.0 or greater and a tip ratio of greater than about 0.2. The filaments may be used as-spun as a spin-oriented feed yarn or as a direct use yarn. The multifilament yarns made from these filaments are useful to make articles with subdued luster and low glitter.