Abstract: A decoder for selected linear error correcting codes, such as a BCH code, uses relatively low-speed circuitry to determine syndromes and corresponding error locations for correcting the code. In a specific embodiment of a BCH linear cyclic invariant error correcting code, only cyclic invariants are stored in Read Only Memory such that the storage requirements of the Read Only Memory are minimized, and table look-up techniques are employed to speed apparent computation. In another specific embodiment of a linear error correcting codes, a Read Only Memory is used to store precomputed indicia of possible errors in the code word, and table look-up techniques are employed to determine one or more syndromes. The table look-up method avoids the complexity of error locating polynomials, algebraic root finders and real-time computation while reducing computation time.