Abstract: Methods and systems for partitioning a device to optimize power consumption are disclosed and may include partitioning circuitry within an integrated circuit into a plurality of power domains, wherein each of the domains includes different power consumption and handling requirements and a processor. A processor in one of the domains may handle processing of tasks internal to that domain. A processor in the first domain may handle processing of tasks in a second of the domains. The processor in each of the domains may be communicatively coupled to one or more common busses, which may be shared by each of the domains. One domain may be powered in a continuous mode and may include low leakage circuitry. The processors may include general purpose processors. A processor in one domain may control image processing circuitry, which may comprise image sensor pipeline, 3D pipeline and/or video accelerator circuitry.

Abstract: A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.

Abstract: A cover insert for spanning a gap between two boards in a decking, in particular a scaffold decking, to prevent objects from falling through said gap and causing injury comprises first and second substantially parallel side walls (10, 11) for fitting into the gap and a cover portion (7) arranged for covering the space between the side walls. One of the side walls (10) has a pair of laterally extending walls (9, 13) extending outwardly in a direction away from the other of the side walls, the laterally extending walls (9, 13) being spaced apart for receiving an edge of one of the boards. A top one of the laterally extending walls (13), that may be an extension of the cover portion (7), provides a flange that rests on the top of the board on one side of the gap, and the cover portion (7) may also extend on the other side to provide a second flange (14) to rest on the top of the board on the other side of the gap.

Abstract: Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.

Abstract: Electron transport material and methods of N-type doping the same are provided.

Abstract: A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.

Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grou

Abstract: A processor comprising: a scalar processing unit for executing scalar instructions each defining a single value pair; a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of value processing units each operable to process one of said multiple value pairs and to generate a respective result; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit.

Abstract: Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.

Abstract: Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may be specified as an address and a format such as a row, a column, or a neighborhood relative to the address.

Abstract: A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.

Abstract: Certain embodiments of the invention may be found in a method for integrated circuit supporting auto-sense of voltage for drive strength adjustment. The method may comprise detecting an input voltage received at an auto-sense pad integrated on a mobile multimedia processing (MMP) chip. The input voltage may be a power supply voltage of the peripheral device received during power-up of the MMP chip, power-up of the peripheral circuitry, and/or dynamically while the MMP is powered-up. The auto-sense pad may adjust drive strength of at least one other pad, which may be an output pad or a bidirectional pad, integrated on the MMP chip may be configured to operate using the determined output voltage. A rise time and/or fall time of signals output by the MMP chip may be varied by the adjustment of the drive strength.

Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

Abstract: Certain aspects of a method and system for protecting data during mobile communication may comprise a mobile multimedia processor that decrypts an encrypted algorithm in hardware within the mobile multimedia processor. The mobile multimedia processor may be adapted to utilize the decrypted algorithm to decrypt data in software. The mobile multimedia processor may be adapted to decrypt instructions for the encrypted algorithm as the instructions enter an instruction cache. The mobile multimedia processor may be adapted to protect the decrypted data by performing a hash operation of the decrypted data and check a result of the hash operation.

Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grou

Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grou

Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

Abstract: A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.

Abstract: A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.