Abstract: A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the invention only models latches as connected to an integrated switch to be powergated. In addition, a fence circuit attached to the powergated macro is modeled as including an extra control signal to force a powergated state of the powergated macro into the fence circuit.

Abstract: A method for synthesizing aggregate data types, in accordance with the present invention, includes representing aggregate data types in a control data flow graph, by representing aggregate objects as operand nodes, and operations on the aggregate objects as operation nodes. One-dimensional bit vectors are formed for the operand nodes, by recursively traversing through fields of the aggregate data type associated with the aggregate objects. Read and write operation nodes are formed in the control data flow graph for representing language constructs for accessing the aggregate objects. The control data flow graph is mapped onto hardware.