Patents by Inventor Stephen Begg

Stephen Begg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7873203
    Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: January 18, 2011
    Assignee: Semiconductor Insights Inc.
    Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
  • Patent number: 7643665
    Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: January 5, 2010
    Assignee: Semiconductor Insights Inc.
    Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
  • Patent number: 7580557
    Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: August 25, 2009
    Assignee: Semiconductor Insights Inc.
    Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
  • Publication number: 20080317328
    Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
    Type: Application
    Filed: August 29, 2008
    Publication date: December 25, 2008
    Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
  • Publication number: 20080317327
    Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
    Type: Application
    Filed: August 29, 2008
    Publication date: December 25, 2008
    Inventors: Vyacheslav L. Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
  • Publication number: 20070256037
    Abstract: The present invention provides an accurate and efficient method of organizing circuitry from a net-list of an integrated circuit, by the steps of generating a reference pattern; identifying the potential matches in the net-list using inexact graph matching; further analyzing the matches to determine if they match the reference pattern; and organizing the net-list into a hierarchy by replacing the identified instances with higher-level representations.
    Type: Application
    Filed: April 26, 2006
    Publication date: November 1, 2007
    Inventors: Vyacheslav Zavadsky, Edward Keyes, Sergei Sourjko, Val Gont, Stephen Begg, Jason Abt
  • Patent number: 7278121
    Abstract: The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: October 2, 2007
    Assignee: Semiconductor Insights Inc.
    Inventors: Elmehdi Aitnouri, Edward Keyes, Stephen Begg, Val Gont, Dale McIntyre, Mohammed Ouali, Vyacheslav Zavadsky
  • Patent number: 7207018
    Abstract: The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: April 17, 2007
    Assignee: Semiconductor Insights Inc.
    Inventors: Vyacheslav L. Zavadsky, Elmehdi Aitnouri, Edward Keyes, Jason Abt, Val Gont, Stephen Begg
  • Publication number: 20060045325
    Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 2, 2006
    Inventors: Vyacheslav Zavadsky, Val Gont, Edward Keyes, Jason Abt, Stephen Begg
  • Publication number: 20060041849
    Abstract: The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.
    Type: Application
    Filed: August 23, 2004
    Publication date: February 23, 2006
    Applicant: Semiconductor Insights Inc.
    Inventors: Elmehdi Aitnouri, Edward Keyes, Stephen Begg, Val Gont, Dale Mclntyre, Mohammed Ouali, Vyacheslav Zavadsky
  • Publication number: 20060031792
    Abstract: The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm.
    Type: Application
    Filed: August 4, 2004
    Publication date: February 9, 2006
    Applicant: Semiconductor Insights Inc.
    Inventors: Vyacheslav Zavadsky, Elmehdi Aitnouri, Edward Keyes, Jason Abt, Val Gont, Stephen Begg
  • Patent number: 6907583
    Abstract: A method and apparatus for extracting circuit design information from a pre-existing semiconductor integrated circuit (IC) or at least a portion thereof is described. It includes imaging at least a portion of two or more physical layers of the pre-existing IC to obtain stored electronic images of the physical IC layers, converting the stored electronic images of the physical IC layers to a vector format data, horizontally and vertically aligning the vector format data of the electronic stored images of the physical IC layers, and providing a multi-layer display of the aligned vector format data. A net-list or schematic is generated from the multi-layer display of the vector format data. The net-list and/or schematic may be generated as a number of individual pages by providing a template of circuit elements and placing a circuit element over a portion of the display corresponding to the circuit element. The template of circuit elements may include transistors, logic gates or complex circuit blocks.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: June 14, 2005
    Assignee: Semiconductor Insights, Inc.
    Inventors: Jason Abt, Thomas Kapler, Stephen Begg
  • Publication number: 20030084409
    Abstract: A method and apparatus for extracting circuit design information from a pre-existing semiconductor integrated circuit (IC) or at least a portion thereof is described. It includes imaging at least a portion of two or more physical layers of the pre-existing IC to obtain stored electronic images of the physical IC layers, converting the stored electronic images of the physical IC layers to a vector format, horizontally and vertically aligning the vector format data of the electronic images of the physical IC layers, and providing a multi-layer display of the aligned vector data. A net-list or schematic is generated from the multi-layer display of the vector data. The netlist and/or schematic may be generated as a number of individual pages by providing a template of circuit elements and placing a circuit element over a portion of the display corresponding to the circuit element. The template of circuit elements may include transistors, logic gates or complex circuit blocks.
    Type: Application
    Filed: October 10, 2002
    Publication date: May 1, 2003
    Applicant: Semiconductor Insights, Inc.
    Inventors: Jason Abt, Thomas Kapler, Stephen Begg
  • Patent number: 5853668
    Abstract: A first reactant is immobilized i.e. in a porous matrix (50), adjacent a sample electrode (46) within a reaction chamber. Energizing of the electrode (46) electrophoretically attracts a mobile second reactant and/or electrolytically induces appropriate reaction conditions to enhance reaction of the first and second reactants. Polarity reversals between the sample electrode (46) and remote electrodes (38), (42), (44) cause unreacted second reactant and/or by-products to migrate away from the immobilized first reactant. The techniques are useful for sequential chemical reactions such as sequencing or construction of proteins, polysaccharides and nucleic acids where cyclical additions and removals of reactants are required. The techniques are amenable to automated micro and nano scale construction and operation and allow direct electrophoretic (38) interfacing with chromatographic, HPCE and mass spectrophotometric equipment.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: December 29, 1998
    Assignee: Ludwig Institute for Cancer Research
    Inventors: Geoffrey Stephen Begg, Richard John Simpson, Antony Wilks Burgess
  • Patent number: 5681751
    Abstract: A first reactant is immobilized i.e. in a porous matrix (50), adjacent a sample electrode (46) within a reaction chamber. Energizing of the electrode (46) electrophoretically attracts a mobile second reactant and/or electrolytically induces appropriate reaction conditions to enhance reaction of the first and second reactants. Polarity reversals between the sample electrode (46) and remote electrodes (38), (42), (44) cause unreacted second reactant and/or by-products to migrate away from the immobilized first reactant. The techniques are useful for sequential chemical reactions such as sequencing or construction of proteins, polysaccharides and nucleic acids where cyclical additions and removals of reactants are required. The techniques are amenable to automated micro and nano scale construction and operation and allow direct electrophoretic (38) interfacing with chromatographic, HPCE and mass spectrophotometric equipment.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: October 28, 1997
    Assignee: Ludwig Institute for Cancer Research
    Inventors: Geoffrey Stephen Begg, Richard John Simpson, Antony Wilks Burgess