Patents by Inventor Stephen Bilotta

Stephen Bilotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor feedback capacitance reduction
    Patent number: 12563758
    Abstract: The reduction of feedback capacitance in active semiconductor devices, such as the reduction in collector to base capacitance in transistors, is described. In one example, a transistor includes a substrate, an active region of the transistor in the substrate, a dielectric layer over a top surface of the substrate, and an interconnect region. The active region includes a base contact over the active region. The interconnect region includes a conductive interconnect that extends over the dielectric layer and is electrically coupled with the base contact. The interconnect region also includes a semiconductor junction region extending under the conductive interconnect in an area of the substrate outside of the active region. The addition of the semiconductor junction region under the conductive interconnect reduces the total collector to base capacitance in the transistor.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: February 24, 2026
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Debdas Pal, Parshant Kumar, Stephen Bilotta, Timothy E. Boles
  • TRANSISTOR FEEDBACK CAPACITANCE REDUCTION
    Publication number: 20240363742
    Abstract: The reduction of feedback capacitance in active semiconductor devices, such as the reduction in collector to base capacitance in transistors, is described. In one example, a transistor includes a substrate, an active region of the transistor in the substrate, a dielectric layer over a top surface of the substrate, and an interconnect region. The active region includes a base contact over the active region. The interconnect region includes a conductive interconnect that extends over the dielectric layer and is electrically coupled with the base contact. The interconnect region also includes a semiconductor junction region extending under the conductive interconnect in an area of the substrate outside of the active region. The addition of the semiconductor junction region under the conductive interconnect reduces the total collector to base capacitance in the transistor.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Debdas Pal, Parshant Kumar, Stephen Bilotta, Timothy E. Boles