Abstract: A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image.

Abstract: Provided are a method, system, deployment and article of manufacture, wherein in one embodiment, a mode of operation may be switched to a service mode by detecting a device inserted into a connector of an input/output port of a system. In the illustrated embodiment, the device has a connector and a wire which loops a code received from the input/output port back to the input/output port. Upon detecting receipt of the transmitted code, the mode of operation may be switched to a service mode. Other embodiments are described and claimed.

Abstract: Provided are a method, system, deployment and article of manufacture, wherein in one embodiment, a mode of operation may be switched to a service mode by detecting a device inserted into a connector of an input/output port of a system. In the illustrated embodiment, the device has a connector and a wire which loops a code received from the input/output port back to the input/output port. Upon detecting receipt of the transmitted code, the mode of operation may be switched to a service mode. Other embodiments are described and claimed.

Abstract: A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image.

Abstract: In one embodiment, a first processor of a multiprocessor system, encounters an exception and jumps to exception handler code at an architecture-defined exception vector. The processor is directed to a data structure which provides a programmable exception vector to additional exception handler code. This additional code may be executed as if it were located at the architecture-defined exception vector. Other embodiments are described and claimed.

Abstract: In managing multiprocessor operations, a first processor repetitively reads a cache line wherein the cache line is cached from a line of a shared memory of resources shared by both the first processor and a second processor. Coherency is maintained between the shared memory line and the cache line in accordance with a cache coherency protocol. In one aspect, the repetitive cache line reading occupies the first processor and inhibits the first processor from accessing the shared resources. In another aspect, upon completion of operations by the second processor involving the shared resources, the second processor writes data to the shared memory line to signal to the first processor that the shared resources may be accessed by the first processor. In response, the first processor changes the state of the cache line in accordance with the cache coherency protocol and reads the data written by the second processor. Other embodiments are described and claimed.

Abstract: Provided are a method, system, deployment and article of manufacture, wherein in one embodiment, a mode of operation may be switched to a service mode by detecting a device inserted into a connector of an input/output port of a system. In the illustrated embodiment, the device has a connector and a wire which loops a code received from the input/output port back to the input/output port. Upon detecting receipt of the transmitted code, the mode of operation may be switched to a service mode. Other embodiments are described and claimed.

Abstract: An apparatus, system, and method are disclosed for flushing cache data in a cache system. The apparatus includes a zero module and a flush module. The zero module executes an internal processor instruction to zero out a zero memory segment of a nonvolatile memory and a processor cache in response to a loss of primary power to the processor cache. The flush module flushes modified data from an address in the processor cache to a flush memory segment of the nonvolatile memory before the zero module puts a zero in the address. Advantageously, the zero memory segment is reserved within the memory and used to zero out the processor cache, effectively flushing the existing data from the processor cache to a flush memory segment of the memory.

Abstract: A method to enable a user mode process to operate in a privileged execution mode is disclosed. Applicants' method provides an operating system comprising a privileged execution mode and a non-privileged execution mode, and a plurality of user mode strings operating in the non-privileged execution mode. The computing device receives a request from a first user mode string to operate in the privileged execution mode to perform one or more designated tasks. Applicants' method authorizes the first user mode string to operate in the privileged execution mode, and the first user mode string performs those one or more designated tasks using the privileged execution mode. Applicants' method continues to permit the first user mode string to operate in the privileged execution mode after completion of the one or more designated tasks.

Abstract: An apparatus, system, and method are provided for updating a code image. The apparatus, system, and method include a loader for loading a new code image into a temporary memory location separate from the memory location occupied by the old code image. A conversion module of the new code image executes and selectively reconciles incompatibilities between the old code image and the new code image. In one aspect, once incompatibilities are reconciled, a copy module copies the new code image into the memory space occupied by the old code image.