Abstract: A barbecue grill smoker assembly includes a firebox base and fuel grate handles and food grate handles connected to components internal to a cooking chamber of the grill smoker that extend outwardly beyond the cooking chamber. The grill smoker assembly includes a fuel grate assembly in the form of a basket that, when combined with a food grate assembly, contains solid fuel within an area defined by a compartment. Fuel can be managed by manipulating the food grate assembly and the fuel grate assembly. The fuel grate assembly may include an aperture to facilitate transfer of residual solid fuel to a charcoal starting device. The lid features a lid support to support the lid when inverted.

Abstract: A barbecue grill smoker assembly (10) is disclosed including fuel grate handles (21) and food grate handles (31) connected to components internal to the cooking chamber of the grill smoker defined by the firebox base (11) but extending outward beyond the cooking chamber in order to allow for manipulation of the components within the grill smoker using clean and cool handles. The grill smoker assembly also includes a fuel grate assembly (30) in the form of a basket that, when combined with the food grate assembly (20), the solid fuel is contained within the area defined by the grate. This enables the fuel to be managed by manipulating the food grate assembly (20) and fuel grate assembly (30). The fuel grate assembly (30) may also include an aperture to facilitate transfer of residual solid fuel to a charcoal starting device.

Abstract: A controller, a memory device including a memory array, and a method for accessing the memory device. The method includes, during a first access, activating a first page of the memory array corresponding to a first row address and accessing data from the first page with a first column address. The method further includes, during a second access, activating a first sub-page of the memory array corresponding to a second row address and accessing data from the first sub-page with a second column address. The activated first sub-page of the memory array is smaller than the first page of the memory array. The method further includes activating a second sub-page without receiving a separate activate command.

Abstract: A controller, a memory device including a memory array, and a method for accessing the memory device. The method includes, during a first access, activating a first page of the memory array corresponding to a first row address and accessing data from the first page with a first column address. The method further includes, during a second access, activating a first sub-page of the memory array corresponding to a second row address and accessing data from the first sub-page with a second column address. The activated first sub-page of the memory array is smaller than the first page of the memory array. The method further includes activating a second sub-page without receiving a separate activate command.

Abstract: A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense amplifier, and a control circuit. The control circuit is configured to isolate the sense amplifier from at least one of the first dynamic random access memory cell and the second dynamic random access memory cell in an idle state and to couple the sense amplifier to only the second dynamic random access memory cell to be refreshed in a refresh state.

Abstract: Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The device temperature may be measured directly, for example, via an on-chip temperature sensor, or may be supplied as bits in a mode register containing temperature information.

Abstract: A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense amplifier, and a control circuit. The control circuit is configured to isolate the sense amplifier from at least one of the first dynamic random access memory cell and the second dynamic random access memory cell in an idle state and to couple the sense amplifier to only the second dynamic random access memory cell to be refreshed in a refresh state.

Abstract: An oscillator circuit includes a capacitor device, a current source for supplying a current to the capacitor device, a reference voltage, and a control circuit. The reference voltage is a first input to a comparator. An output of the capacitor device and an output of the current source are a second input to the comparator. The control circuit resets the oscillator circuit when the first and second inputs to the comparator are equal.

Abstract: The present invention includes an error correction circuit with a data memory, a write tree, a parity memory, and a read tree. The data memory is configured to hold a set of data. The write tree is configured to receive the set of data and to generate parity data. The parity memory is coupled to the write tree and is configured to receive and hold parity data. The read tree is configured to receive data from the data memory and parity data from the parity memory. The read tree is configured to generate an indication of whether an error has occurred in the data during storage within the data memory.

Abstract: A system and method for refreshing data in a dynamic random access memory (“DRAM”) is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal communication with the data memory for translating an internal address of each of the plurality of memory banks into a corresponding external address, a map comparator in signal communication with the map memory for selectively enabling a memory bank in accordance with its external address, a refresh address generator in signal communication with the map comparator for selectively refreshing the enabled memory bank in accordance with its external address, and a refresh counter in signal communication with the refresh address generator for signaling a refresh in accordance with the maximum required refresh time of the enabled memory bank; and where the corresponding method includes determining the maximum required refresh period for each of the memory banks, respectively, prioritizing the memory banks in accordance wit

Abstract: An oscillator circuit includes a capacitor device, a current source for supplying a current to the capacitor device, a reference voltage, and a control circuit. The reference voltage is a first input to a comparator. An output of the capacitor device and an output of the current source are a second input to the comparator. The control circuit resets the oscillator circuit when the first and second inputs to the comparator are equal.

Abstract: Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The device temperature may be measured directly, for example, via an on-chip temperature sensor, or may be supplied as bits in a mode register containing temperature information.

Abstract: A system and method for refreshing data in a dynamic random access memory (“DRAM”) is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal communication with the data memory for translating an internal address of each of the plurality of memory banks into a corresponding external address, a map comparator in signal communication with the map memory for selectively enabling a memory bank in accordance with its external address, a refresh address generator in signal communication with the map comparator for selectively refreshing the enabled memory bank in accordance with its external address, and a refresh counter in signal communication with the refresh address generator for signaling a refresh in accordance with the maximum required refresh time of the enabled memory bank; and where the corresponding method includes determining the maximum required refresh period for each of the memory banks, respectively, prioritizing the memory banks in ac