Abstract: A tandem photovoltaic (PV) may include III-V semiconductors, silicon, a cathode electrode, an anode electrode, and a gold-to-gold metal bridge electrode. The semiconductors include p-typed and n-typed regions. To form a tandem PV structure, bottom and top PV cells can be independently fabricated. The bottom and the top PV cells are electrically connected by the gold-to-gold metal bridge interconnection, which is positioned between the bottom and the top PV cells. The metal bridge may be formed by cold-welding compression technique. This structure is compatible to the development of tandem PVs as well as thermophotovoltaic (TPV) cells.

Abstract: A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each of the virtual address received, the selection unit positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs.

Abstract: A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification. Two different serialization fence instructions are illustrated: a data memory reference serialization fence instruction (SRLZ.d) and an instruction fetch serialization fence instruction (SRLZ.i). The data memory reference serialization fence instruction ensures that subsequent instruction executions and data memory references will observe the effects of the control register write. The instruction fetch serialization fence instruction ensures that the entire machine pipeline, starting at the initial instruction fetch stage, will observe the effects of the control register write.