Abstract: A lightwave telecommunications matrix configuration for use in a fiber-optic telecommunications network includes a first set of interface circuits for interfacing with a first external fiber-optic circuit. A second set of interface circuits interfacing with a second external fiber-optic circuit. A plurality of time slot matrices associate between the first and second sets of interface circuits for routing lightwave transmissions within the fiber-optic network. The matrix configuration is optimized for a variety of telecommunication switch architectures, including add/drop matrix, ring, and terminal configurations. Accordingly, the matrix configuration is easily scalable to a wide range of telecommunications network sizes and data rates.

Abstract: Working DS3/STS interface cards (18, 46) receive DS3 traffic on incoming DS3 communication lines (12, 42). The interface cards (18, 46) are operable to translate the DS3 signals into STS signals, and to "stuff" them into "A" and "B" clock frames provided to them by an "A" formatter (70) and a "B" formatter (74). These clock frames are then used to transmit data to the "A" formatter (70) and the "B" formatter (74). The DS3/STS interface cards (18,46) inspect incoming STS signals on "A" and "B" buses (82, 84) without having to switch to the inspected signal. Formatters 70 and 74 translate the STS data into formatted data, which eventually are transmitted in optical form on respective optical fibers (150, 190) at clock rates which do not have to be the same. Regeneration input and output ports ( 210, 216, 206, 166) allow the through-communication of telecommunications signals in STS format, obviating the need for down-translation to DS3 format and back-translation to STS format.

Abstract: In a plurality of working interface circuits (12-19), each circuit has at least one transmitter (86) and at least one receiver (88). A spare interface circuit (35) has at least one transmitter (158) and at least one receiver (154). A switch circuit (21) is coupled to the working interface circuits (12-19) and the spare interface circuit (35) and includes a plurality of switches (110-117; 109; 122, 138, 130, 150) which are operable to create a selected one of at least two data paths. A first of these data paths may be selectively formed from a selected one of the working interface circuits (12-19) to the spare interface circuit (35) to monitor the operation of the selected one of the working interface circuits (12-19) without affecting any communications signal transmitted by that working interface circuit. Another data path may be selectively established from a malfunctioning one of the working interface circuits (12-19) to the spare interface circuit (35).

Abstract: High speed telecommunications interface circuitry (10) receives a plurality of incoming telecommunication channels (11), and includes a plurality of working receivers (88) each having an input (83-85) connected to a respective one of the incoming channels (11) . A switching circuit (21) has a plurality of working circuit ports (112-116) each connected to an input (83-85) of a respective one of the working receivers (88). The switching circuit has a spare circuit port (33), and is operable to create a data path between the selected one of the working circuit ports (112-116) and the spare circuit port (33). A spare receiver (88) has an input (128) connected to the spare circuit port (33) of the switching circuit (21). Preferably, a switch card (21) of the switching circuit also includes a plurality of series-connected switches (254-268) which are operable to create a single switching path from a selected one of a plurality of working circuit output ports on the switch card (21) to a spare circuit port (36).

Abstract: A low inductance shielded cable connector to printed circuit interface with an isolated chassis ground can be obtained by a multilayer printed circuit board and plated-through holes. Two or more layers of the printed circuit board are used to provide a capacitive connection to chassis ground and other layers are used to provide connections for signal ground (cable ground) and signal connector leads. The direct contact of the shielded cable connector to a multiplicity of points on the exterior layer of the printed circuit board, wherein the contact points completely encircle the signal conductor, substantially eliminates both radiation of signal and pickup of signals by the signal conductor.

Abstract: A serial bit stream and a clock signal at a frequency equal to the bit rate divided by an integer n are passed in opposite directions via respective delay lines to respectively the data and clock inputs of n flip-flops, which thereby each latch a respective one of n bits of the bit stream during n/2 bit periods. During the next n/2 bit periods the outputs of the flip-flops are stable, and the n bits are latched in a parallel data latch. The delay lines comprise transmission lines terminated with their effective characteristic impedances. The converter is particularly useful for bit rates greater than 1Gb/s.