Abstract: An electronic device may be surrounded by an exterior region and may have an interior region. Electronic components may be mounted in the interior region. Housing walls such as housing walls formed from transparent layers of material may separate the interior region from the exterior region. A display may be visible through one of the transparent layers of material. A transparent layer of material may be coupled to housing structures in the device and may be formed of glass or glass-ceramic. The transparent layer may have two opposing chemically strengthened surface layers of different thicknesses. A coating may be formed on a thinner of the two opposing chemically strengthened surface layers. The coating may have an oleophobic outer coating layer, an antireflection layer, and an antiscratch layer. The antiscratch layer may have one or more compressively stressed dielectric layers and may have one or more corresponding graded composition layers.

Abstract: An electronic device may have a display cover layer provided with an infrared-transparent antireflection coating. A pixel array may emit visible light through the cover layer and the coating. An infrared emitter may emit infrared light and an infrared sensor may receive infrared light through the coating and the cover layer. The coating may include a stack of thin-film interference layers. The stack may include alternating lower and higher refractive index layers. The layers may have thicknesses and materials that configure the coating to exhibit an infrared transmittance of greater than 94% from 920 nm to 960 nm and a photopic reflectance of less than 1.5%. The coating may reflect visible light to prevent displayed images from being obscured by visible reflections. At the same time, some photopic reflectance of the coating may be sacrificed to maximize infrared transmittance and accommodate operation by the infrared emitter and sensor.

Abstract: An electronic device may have a display cover layer provided with an infrared-transparent antireflection coating. A pixel array may emit visible light through the cover layer and the coating. An infrared emitter may emit infrared light and an infrared sensor may receive infrared light through the coating and the cover layer. The coating may include a stack of thin-film interference layers. The stack may include alternating lower and higher refractive index layers. The layers may have thicknesses and materials that configure the coating to exhibit an infrared transmittance of greater than 94% from 920 nm to 960 nm and a photopic reflectance of less than 1.5%. The coating may reflect visible light to prevent displayed images from being obscured by visible reflections. At the same time, some photopic reflectance of the coating may be sacrificed to maximize infrared transmittance and accommodate operation by the infrared emitter and sensor.

Abstract: An electronic device may have transparent members such as display cover layers and camera windows. A transparent member such as a sapphire member may be provided with an antireflection coating. The antireflection coating may have a stack of dielectric thin-film interference filter layers that form a thin-film interference filter that suppresses visible light reflections. The stack of dielectric thin-film interference filter layers may have thicknesses and materials that provide the thin-film interference filter and coating with low light reflection properties while enhancing scratch resistance. An adhesion layer may be used to help adhere the stack of thin-film interference filter layer to the transparent member. An antismudge coating such as a fluoropolymer coating may be used to reduce smudging. Graded layers and layers with elevated hardness values may be used in the coating.

Abstract: An electronic device may have transparent members such as display cover layers and camera windows. A transparent member such as a sapphire member may be provided with an antireflection coating. The antireflection coating may have a stack of dielectric thin-film interference filter layers that form a thin-film interference filter that suppresses visible light reflections. The stack of dielectric thin-film interference filter layers may have thicknesses and materials that provide the thin-film interference filter and coating with low light reflection properties while enhancing scratch resistance. An adhesion layer may be used to help adhere the stack of thin-film interference filter layer to the transparent member. An antismudge coating such as a fluoropolymer coating may be used to reduce smudging. Graded layers and layers with elevated hardness values may be used in the coating.

Abstract: An electronic device may have transparent members such as display cover layers and camera windows. A transparent member such as a sapphire member may be provided with an antireflection coating. The antireflection coating may have a stack of dielectric thin-film interference filter layers that form a thin-film interference filter that suppresses visible light reflections. The stack of dielectric thin-film interference filter layers may have thicknesses and materials that provide the thin-film interference filter and coating with low light reflection properties while enhancing scratch resistance. An adhesion layer may be used to help adhere the stack of thin-film interference filter layer to the transparent member. An antismudge coating such as a fluoropolymer coating may be used to reduce smudging. Graded layers and layers with elevated hardness values may be used in the coating.

Abstract: A giant magnetoresistive stack (10) for use in a magnetic read head includes a NiFeCr seed layer (12), a ferromagnetic free layer (14), a nonmagnetic spacer layer (16), a ferromagnetic pinned layer (18), and a PtMnX pinning layer (20), where X is either Cr or Pd. The ferromagnetic free layer (14) has a rotatable magnetic moment and is positioned adjacent to the NiFeCr seed layer (12). The ferromagnetic pinned layer (18) has a fixed magnetic moment and is positioned adjacent to the PtMnX pinning layer (20). The nonmagnetic spacer layer (16) is positioned between the free layer (14) and the pinned layer (18).