Abstract: A serializer-deserializer (SERDES) includes a clock-data recovery block, a control block, and a low-pass filter. The control block contains a state machine that includes a fast convergence mode utilizing an unstable operating point and a slow tracking mode utilizing a stable operating point. The control block is configured to start in the fast convergence mode to allow quickly locking the recovered clock to the incoming data stream by replicating movement commands resulting in multiple phase adjustments for each transition. To facilitate proper operation of the SERDES, the fast convergence mode is exited after N-bits and a slow tracking mode is entered to provide stable operation. The control block accepts filtered transition-data and data-transition phase state signals and converges to a phase aligned state in less than 2N-bits where N represents the number of phases in one data bit.

Abstract: A serializer-deserializer (SERDES) includes a clock-data recovery block, a control block, and a low-pass filter. The control block contains a state machine that includes a fast convergence mode utilizing an unstable operating point and a slow tracking mode utilizing a stable operating point. The control block is configured to start in the fast convergence mode to allow quickly locking the recovered clock to the incoming data stream by replicating movement commands resulting in multiple phase adjustments for each transition. To facilitate proper operation of the SERDES, the fast convergence mode is exited after N-bits and a slow tracking mode is entered to provide stable operation. The control block accepts filtered transition-data and data-transition phase state signals and converges to a phase aligned state in less than 2N-bits where N represents the number of phases in one data bit.

Abstract: A single-ended sense amplifier pre-charges the data output line of a bank of memory cells or register file to approximately the switch point of an inverter that is part of a buffer, in preparation for the next data read cycle. The amplifier includes a stack of six transistors connected in series between a supply voltage and ground. The memory output is connected to the stack mid-point, to a latch input and to a buffer input. The most recent binary logic level read from memory passes through the latch. The latch and stack are then clocked, and the three-transistor portion of the stack turned on pulls the voltage on the stack mid-point to approximately one-half the supply voltage, which is the buffer inverter switch point. The stack is then turned off, and the stack mid-point floats at that voltage value in preparation for the next read cycle. As such, the common data line needs only slew a relatively small amount of voltage during the next read cycle.