Abstract: A flexible lighting fixture includes an elongate channel having a bottom, opposing sides, first and second ends. An elongate electroluminescent lamp, having first and second ends, is disposed in the channel, between the opposing sides, with the first end generally adjacent the first end of the channel and the second end generally adjacent the second end of the channel. The electroluminescent lamp has contacts at the first end thereof, with wire leads connected to contacts on the electroluminescent lamp. A translucent cover is mounted in the channel, over the over the electrohiminescent lamp, and is engaged by the opposing sides of the channel. An encapsulant in the first end of the channel secures the first end of the electroluminescent lamp in the channel, but the remainder of the electroluminescent lamp is unattached to the channel so that when the fixture flexes, the remainder of the electroluminescent lamp can slide relative to the channel.

Abstract: A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.

Abstract: A serial transport frame format is described which transfers data between two locations. The serial transport frame format comprises a fixed number of channels per frame, each channel having a predetermined size. One channel per frame contains frame synchronization information and each channel which conveys data, contains a first portion for the transfer of data and a second portion which contains associated control information.

Abstract: A telephone switching network is disclosed, which network is adapted to provide connections between a plurality of input subscriber lines. The network includes a time slot interchanger which comprises a transmit switch memory and a receive switch memory. The transmit and receive memories are capable of storing data at addressable storage locations, which data is indicative of digital data to be transmitted from a line circuit and digital data to be received by a line circuit during a connection between the two line circuits. A connect memory is also employed for storing data indicative of connections to be made between line circuits. The connect memory as well as the switch memories are controlled in operation by a processor, which processor includes an access control means.

Abstract: An elastic storage circuit employs a first in/first out (FIFO) memory which stores data contained in a serial stream in a plurality of locations, each of which is associated with a unique address. The storage locations operate to store both the data and the address. A word address counter generates a five bit address code to accompany the data bits as stored in the FIFO. If a chronic increase or decrease in the frequency rate of the data occurs, the FIFO will overflow or underflow. This condition is detected by suitable detectors which create an alarm to completely reset the entire contents of the memory and to refill a portion of the memory over a given interval sufficient to permit the system to recover from the slip in the data rate and to thereafter synchronously read the data together with the address identification from the FIFO.