Abstract: A method and apparatus for acquiring a signal employing a coherent timebase are provided. The method comprises the steps of defining a pattern length count of a repetitive pattern in a signal to be acquired, defining a number of samples per unit interval, and providing data strobes synchronous to a coherent timebase. An arbitrary one of the data strobes is designated as a timing for a potential trigger. A number of subsequent data strobes is counted in accordance with the pattern length count times the samples per unit interval and a portion of the signal corresponding to the pattern length count times the samples per unit interval is acquired beginning at a point in the signal defined by the designated arbitrary data strobe.

Abstract: A method for synchronizing a plurality of sub-systems, comprising the steps of measuring a relationship between a divider associated with each of the plurality of sub-systems; and adjusting a phase of one or more of the dividers to a known relationship with one of the dividers. A command is issued synchronous to a divider associated with one of the plurality of sub-systems. The command is received at one of the sub-systems and is acted upon synchronous to a divider associated with the one of the sub-system receiving said command.

Abstract: A method for synchronizing a plurality of sub-systems, comprising the steps of measuring a relationship between a divider associated with each of the plurality of sub-systems; and adjusting a phase of one or more of the dividers to a known relationship with one of the dividers. A command is issued synchronous to a divider associated with one of the plurality of sub-systems. The command is received at one of the sub-systems and is acted upon synchronous to a divider associated with the one of the sub-system receiving said command.

Abstract: A programmable delay circuit is formed of at least one channel of cascaded, directly coupled inverter elements, the at least one channel including a power supply terminal to which a controllable operating voltage is supplied. The overall time delay exhibited by the at least one channel is a function of the magnitude of the operating voltage supplied to the power supply terminal and the number of cascaded inverter elements included therein. A desired time delay may be established by generating a voltage representing the actual time delay exhibited by the channel, comparing the generated voltage and a reference voltage representing the desired delay, and adjusting the magnitude of the operating voltage supplied to the power supply terminal as a function of the difference between the compared voltages.