Abstract: Electronic device processing systems may include a mainframe housing having a transfer chamber, a first carousel assembly, a second carousel assembly, a first load lock, a second load lock, and a robot adapted to operate in the transfer chamber to exchange substrates between the first and second carousels and the first and second load locks. The robot may include first and second end effectors operable to extend and/or retract simultaneously or sequentially along substantially co-parallel lines of action. Methods and multi-axis robots for transporting substrates are described, as are numerous other aspects.

Abstract: Electronic device processing systems may include a mainframe housing having a transfer chamber, a first carousel assembly, a second carousel assembly, a first load lock, a second load lock, and a robot adapted to operate in the transfer chamber to exchange substrates between the first and second carousels and the first and second load locks. The robot may include first and second end effectors operable to extend and/or retract simultaneously or sequentially along substantially co-parallel lines of action. Methods and multi-axis robots for transporting substrates are described, as are numerous other aspects.

Abstract: A wafer handling system may include upper and lower linked robot arms that may move a wafer along a nonlinear trajectory between chambers of a semiconductor processing system. These features may result in a smaller footprint in which the semiconductor processing system may operate, smaller transfer chambers, smaller openings in process chambers, and smaller slit valves, while maintaining high wafer throughput. In some embodiments, simultaneous fast wafer swaps between two separate chambers, such as load locks and ALD (atomic layer deposition) carousels, may be provided. Methods of wafer handling are also provided, as are other aspects.

Abstract: A wafer handling system may include upper and lower linked robot arms that may move a wafer along a nonlinear trajectory between chambers of a semiconductor processing system. These features may result in a smaller footprint in which the semiconductor processing system may operate, smaller transfer chambers, smaller openings in process chambers, and smaller slit valves, while maintaining high wafer throughput. In some embodiments, simultaneous fast wafer swaps between two separate chambers, such as load locks and ALD (atomic layer deposition) carousels, may be provided. Methods of wafer handling are also provided, as are other aspects.

Abstract: Electronic device processing systems are described. The system includes a mainframe housing having a transfer chamber, a first facet, a second facet opposite the first facet, a third facet, and a fourth facet opposite the third facet, a first carousel assembly coupled to a first facet, a second carousel assembly coupled to the third facet, a first load lock coupled to the second facet, a second load lock coupled to the fourth facet, and a robot adapted to operate in the transfer chamber to exchange substrates from the first and second carousels. Methods and multi-axis robots for transporting substrates are described, as are numerous other aspects.

Abstract: Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.