Patents by Inventor Stephen C. Joy

Stephen C. Joy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7208348
    Abstract: The electrical contacts, such as ball grid array (BGA) solder balls, of an integrated circuit (IC) are coupled to printed circuit board (PCB) bonding pads that include vias. According to an embodiment of an electronic assembly, the vias are formed off-center, so as to inhibit bridging between adjacent solder balls during a solder reflow operation by minimizing the effect of solder ball ballooning resulting from outgassing of a thermally expansive substance, such as a volatile organic compound (VOC) from the via channels. The bonding pads are separated into two groups, each having vias offset in a different direction, so that asymmetric surface tension forces in the molten solder during a solder reflow operation do not cause the IC to slide to one side. A substrate, an electronic assembly, an electronic system, and fabrication methods are also described.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventors: Phil Geng, Stephen C. Joy
  • Patent number: 7036712
    Abstract: The electrical contacts of an integrated circuit package are coupled to printed circuit board bonding pads that include vias having via channels. In one embodiment, a method for fabricating an electronic assembly utilizes a mask having at least one aperture that overlies the bonding pad without substantially overlying the bonding pad's via channel. The aperture can be of any shape, including a circle, ellipse, polygon, or a free-form shape. Solder paste is screened through the mask onto the printed circuit board pads but not the via channels. The electrical contacts of a surface mount technology component such as a ball grid array component can then be affixed to the bonding pads using a reflow soldering technique according to one embodiment.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: May 2, 2006
    Assignee: Intel Corporation
    Inventors: Stephen C. Joy, Dan Shier
  • Patent number: 6833615
    Abstract: The electrical contacts, such as ball grid array (BGA) solder balls, of an integrated circuit are coupled to printed circuit board (PCB) bonding pads that include vias. According to one embodiment of an electronic assembly, the vias are formed off-center, so as to inhibit bridging between adjacent solder balls during a solder reflow operation by minimizing the effect of solder ball ballooning resulting from outgassing of a thermally expansive substance, such as a volatile organic compound (VOC) from the via channels. A substrate and an electronic system are also described.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: December 21, 2004
    Assignee: Intel Corporation
    Inventors: Phil Geng, Stephen C. Joy
  • Publication number: 20020108777
    Abstract: The electrical contacts of an integrated circuit package are coupled to printed circuit board bonding pads that include vias having via channels. In one embodiment, a method for fabricating an electronic assembly utilizes a mask having at least one aperture that overlies the bonding pad without substantially overlying the bonding pad's via channel. The aperture can be of any shape, including a circle, ellipse, polygon, or a free-form shape. Solder paste is screened through the mask onto the printed circuit board pads but not the via channels. The electrical contacts of a surface mount technology component such as a ball grid array component can then be affixed to the bonding pads using a reflow soldering technique according to one embodiment.
    Type: Application
    Filed: April 8, 2002
    Publication date: August 15, 2002
    Applicant: Intel Corporation
    Inventors: Stephen C. Joy, Dan Shier
  • Patent number: 6429389
    Abstract: The electrical contacts of an integrated circuit are coupled to printed circuit board (PCB) bonding pads that include vias. A method for fabricating an electronic assembly utilizes at least one operation in which a thermally expansive substance, such as a volatile organic compound (VOC), is applied to the PCB. Some of the VOC goes into the via channels. The electrical contacts of a surface mount technology component such as a ball grid array (BGA) component are affixed to the bonding pads using a reflow soldering technique. According to one embodiment, the via channels are formed so as to inhibit bridging between adjacent BGAs during a solder reflow operation by minimizing outgassing of the VOC from the via channels. A substrate and an electronic system are also described.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: August 6, 2002
    Assignee: Intel Corporation
    Inventors: Ji Yoon Chung, Stephen C. Joy
  • Publication number: 20020084105
    Abstract: The electrical contacts of an integrated circuit are coupled to printed circuit board (PCB) bonding pads that include vias. A method for fabricating an electronic assembly utilizes at least one operation in which a thermally expansive substance, such as a volatile organic compound (VOC), is applied to the PCB. Some of the VOC goes into the via channels. The electrical contacts of a surface mount technology component such as a ball grid array (BGA) solder ball component are affixed to the bonding pads using a reflow soldering technique. According to one embodiment, the vias are formed off-center, so as to inhibit bridging between adjacent solder balls during a solder reflow operation by minimizing the effect of solder ball ballooning resulting from outgassing of the VOC from the via channels. A substrate and an electronic system are also described.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Phil Geng, Stephen C. Joy
  • Patent number: 6395995
    Abstract: The electrical contacts of an integrated circuit package are coupled to printed circuit board bonding pads that include vias having via channels. In one embodiment, a method for of any shape, including a circle, ellipse, polygon, or a free-form shape. Solder paste is screened through the mask onto the printed circuit board pads but not the via channels. The electrical contacts of a surface mount technology component such as a ball grid array component can then be affixed to the bonding pads using a reflow soldering technique according to one embodiment.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: May 28, 2002
    Assignee: Intel Corporation
    Inventors: Stephen C. Joy, Dan Shier
  • Patent number: 6046909
    Abstract: A card for a computer is described which has a printed circuit board having a substrate which includes a number of layers, and vias extending into the substrate. By configuring the vias correctly they can be used for distributing stresses on the printed circuit board which may result from a combined effect of a change in temperature and a mismatch between thermal coefficients of the printed circuit board and an electronic device mounted to the printed circuit board. The vias may be configured by providing more deep vias which extend through more layers of the substrate, by positioning the deeper vias correctly, and by controlling the dimensions of contact pads which are connected to the vias. By correctly configuring the vias, stresses on the printed circuit board can be reduced to and extent which would allow for a substrate having fewer layers and having larger surface areas.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: April 4, 2000
    Assignee: Intel Corporation
    Inventor: Stephen C. Joy