Abstract: An integrated circuit (100) includes a firewall input terminal, a first circuit (110, 120, 170, 172), and a second circuit (220). The firewall input terminal is for receiving a firewall input signal. The first circuit (110, 120, 170, 172) is coupled to a first power supply voltage terminal (203) and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (210), to the firewall input terminal (214), and to the first circuit (110, 120, 170, 172). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

Abstract: An improved signal line routing scheme includes a plurality of dynamic signal lines disposed in parallel to each other, and a plurality of static signal lines disposed in parallel to each other and also disposed in parallel with the plurality of dynamic signal lines, wherein at least one of the plurality of static signal lines is disposed immediately adjacent to each one of the plurality of dynamic signal lines.

Abstract: A microprocessor having an option to select one of multiple clock frequencies as an internal clock frequency. The microprocessor reconfigures the speed paths of internal function circuit on the basis of a clock selection signal used to select the internal clock frequency. In this manner the minimum number of internal clock cycles are used to carry out the function of the function circuit despite the particular internal frequency selected.

Abstract: The invention facilitates testing of electrical circuitry which includes a circuit receiving a signal asynchronous with respect to the circuit clock. The exact clock pulse on which the asynchronous signal is asserted may be difficult or impossible to predict even when the circuitry inputs are known. However, a range of pulses can be determined during which the asynchronous signal is asserted. The sampling of the asynchronous signal is blocked until the end of the range of pulses. If it is known that at the end of the range of pulses the asynchronous signal should still be asserted provided that the circuitry functions properly, the asynchronous signal is sampled at the end of the range of pulses. Alternatively, if the asynchronous signal can be deasserted by the end of the range of pulses, the assertion of the asynchronous signal is detected and latched by the asynchronous signal pulse detector, and at the end of the range of pulses the circuit samples the value latched by the pulse detector.

Abstract: An apparatus for synchronizing a plurality of asynchronous circuits during testing operations is provided. The apparatus includes first and second clock inputs, a test mode input, and an output. The apparatus receives a first clock signal from a first clock at the first clock input, and a second clock signal from a second clock at the second clock input. Responsive to the state of a test mode signal at the test mode input, the apparatus generates either the first clock signal or the second clock signal at the output. A first circuit is arranged to be driven by the output of the apparatus, while a second circuit is driven by one of the first or second clocks. Consequently, the first and second circuits are driven by different clocks when the test mode signal is in one state, and driven by the same clock when the test mode signal is in another state.