Abstract: A bid invalidating auction system may include a memory, an interface, and a processor. The memory stores a plurality of elements characterized by an ordering in which the elements will be rendered ineligible to win a contest. The processor provides, via the interface, the elements to the users, and receives, via the interface, a selection of an element from a user. The processor associates the element with the user if the element is eligible and not associated with another user. The processor renders the next eligible element in the ordering ineligible, if the first element is associated with the first user. The processor repeats the receive, associate, identify and render until an occurrence of an event. Upon the occurrence of the event, the processor identifies the next eligible element in the ordering which is associated with a user and designates the associated user the winner.