Patents by Inventor Stephen Cadieux

Stephen Cadieux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7925971
    Abstract: A method and apparatus for converting documents from one format to another in a speed efficient way involves a hardware module which implements several operating pipeline stages which work in parallel. The transformations are supplied and decomposed into sequences of control units. The transformation of documents consists of applying control unit sequences to input documents. The control units are themselves executed by a set of dedicated hardware resources. Furthermore the pipeline is capable of operating on more than one document at a time. Fast document transformation is a key capability of document processing systems. The use of parallel processing techniques and hardware that implements highly specialized transformation resources make this invention particularly scalable for its use in large, high speed content networks.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: April 12, 2011
    Assignee: Solace Systems, Inc.
    Inventors: Edward D. Funnekotter, Jason Whelan, Jonathan Bosloy, Patrick Brodeur, Stephen Cadieux, Philippe-Andre Babkine, David W. Horton, Paul Kondrat
  • Patent number: 7318211
    Abstract: A method, system, apparatus, and machine-readable medium for physical placement of an integrated circuit based on the timing constraints are provided. The method involves a two-pass physical placement technique. After the first pass of the physical placements of the blocks and the top level, the timing results of the top level and of each block are analyzed. The method involves the computation of latency per gate per unit area (LPGA) of the block ports of each block. Based on the calculated LPGA, the timing constraints of the blocks are updated. The second pass of physical placement is performed, based on the updated timing constraints.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: January 8, 2008
    Assignee: Cisco Technology, Inc.
    Inventor: Stephen Cadieux
  • Publication number: 20070100920
    Abstract: A method and apparatus for converting documents from one format to another in a speed efficient way involves a hardware module which implements several operating pipeline stages which work in parallel. The transformations are supplied and decomposed into sequences of control units. The transformation of documents consists of applying control unit sequences to input documents. The control units are themselves executed by a set of dedicated hardware resources. Furthermore the pipeline is capable of operating on more than one document at a time. Fast document transformation is a key capability of document processing systems. The use of parallel processing techniques and hardware that implements highly specialized transformation resources make this invention particularly scalable for its use in large, high speed content networks.
    Type: Application
    Filed: October 25, 2006
    Publication date: May 3, 2007
    Applicant: SOLACE SYSTEMS, INC.
    Inventors: Edward Funnekotter, Jason Whelan, Jonathan Bosloy, Patrick Brodeur, Stephen Cadieux, Philippe-Andre Babkine, David Horton, Paul Kondrat
  • Publication number: 20070055952
    Abstract: A method, system, apparatus, and machine-readable medium for physical placement of an integrated circuit based on the timing constraints are provided. The method involves a two-pass physical placement technique. After the first pass of the physical placements of the blocks and the top level, the timing results of the top level and of each block are analyzed. The method involves the computation of latency per gate per unit area (LPGA) of the block ports of each block. Based on the calculated LPGA, the timing constraints of the blocks are updated. The second pass of physical placement is performed, based on the updated timing constraints.
    Type: Application
    Filed: September 6, 2005
    Publication date: March 8, 2007
    Applicant: Cisco Technology, Inc.
    Inventor: Stephen Cadieux