Abstract: A method of testing an integrated circuit design to determine whether or not the design satisfies an electrostatic discharge protection specification, said circuit design incorporating electrostatic discharge protection routes between top-level nodes of the design. The method comprises defining an electrostatic discharge protection score for each of said electrostatic discharge protection routes, for each top-level node pair, calculating an electrostatic discharge score for every route through the active circuit between the top-level nodes, and identifying active circuit routes between top-level node pairs for which the electrostatic discharge score is less than the electrostatic discharge protection score for the corresponding electrostatic discharge protection route, or lies within a predefined amount of that score.