Abstract: A system includes a wellhead system, and a flow control system coupled to the wellhead system. The flow control system includes a housing with a flow path between an inlet and an outlet. The flow control system also includes a flow control device disposed in the housing along the flow path. The flow control system also includes a bonnet assembly surrounding the flow control device. The bonnet assembly is configured to selectively mount one of a manual actuator and a powered actuator to actuate the flow control device.

Abstract: A system, including a wellhead system, and a flow control system coupled to the wellhead system, wherein the flow control system includes a housing with a flow path between an inlet and an outlet, a flow control device disposed in the housing along the flow path, and a bonnet assembly surrounding the flow control device, wherein the bonnet assembly is configured to selectively mount one of a manual actuator and a powered actuator to actuate the flow control device.

Abstract: An imaging system 10 for automatically capturing an image of a faint pattern of light emitted by a specimen comprises: an electronic image capture device 12, such as a camera having a CCD sensor; a light-tight enclosure 24 having within a platform 32 for mounting a light-emitting specimen 30 thereon within the field of view of the image capture device 12; and a computer 50, connected to at least the image capture device 12. The computer 50 is adapted to: estimate a maximum signal level that can be expected from the specimen 30 and calculate, based on said estimated maximum signal level, a peak signal level estimate (psle); calculate an exposure time on the basis of the psle and a desired resolution for a captured image; and capture an image for the calculated exposure time. The desired resolution may a user-selected choice, balancing a need for quality of final image against the time required to capture it. An associated method is also disclosed.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: Methods and systems for treating a waste stream in a waste treatment system involve performing a unit process of the waste treatment system by contacting the waste stream with oxyhydrogen-rich gas generated on-site by an oxyhydrogen gas generator that implements water dissociation technology. The oxyhydrogen gas generator involves applying a pulsed electrical signal to a series of closely-spaced electrodes that are submerged in the waste stream to produce oxyhydrogen-rich gas from a water component of the waste stream. Operation of the oxyhydrogen gas generator in the waste stream may accomplish one or more unit processes for waste treatment, such as oxidation, stripping, floatation, disinfection, conditioning, stabilization, thickening, and dewatering, among others. At least a portion of the oxyhydrogen-rich gas can be conveyed for a second use in the waste treatment system, such as a source of combustible fuel for incineration or power generation, for example.

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: The present invention features vectors that contain a promoter effective for expression in bacterial cells and a promoter effective for expression in insect cells. The dual promoter system allows use of the same vector in both host cell systems so that construction of only a single vector is needed to express a polynucleotide inserted at a downstream cloning site. In preferred embodiments the vector is used to derive a recombinant baculovirus that is used to infect host cells. In particular vectors the promoters are a baculovirus polh promoter and a T7lac promoter. In particular vectors the promoter effective for expression in bacteria is positioned between the promoter effective for expression in insect cells and a cloning site. The invention also features various high throughput screening methods.

Abstract: The present invention provides embodiments of methods and devices for the suppression of copper hillocks. Copper hillocks are suppressed by capping the copper layer with a dielectric film before any significant growth of copper hillocks can begin using a ramped temperature dielectric deposition process. Copper hillocks are also suppressed by doping a copper layer with a dopant that will constrain the grain size of the copper during subsequent processing. These methods are applicable to the construction of MIM capacitors and interconnect structures.

Abstract: The present invention provides embodiments of methods and devices for the suppression of copper hillocks. Copper hillocks are suppressed by capping the copper layer with a dielectric film before any significant growth of copper hillocks can begin using a ramped temperature dielectric deposition process. Copper hillocks are also suppressed by doping a copper layer with a dopant that will constrain the grain size of the copper during subsequent processing. These methods are applicable to the construction of MIM capacitors and interconnect structures.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: The invention relates to a process of forming a compact bipolarjunction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

Abstract: A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.