Patents by Inventor Stephen Chang

Stephen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200227520
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: Kelin J. KUHN, Seiyon KIM, Rafael RIOS, Stephen M. CEA, Martin D. GILES, Annalisa CAPPELLANI, Titash RAKSHIT, Peter CHANG, Willy RACHMADY
  • Patent number: 10711288
    Abstract: The disclosure relates to omega-hydroxylated fatty acid derivatives and methods of producing them. Herein, the disclosure encompasses a novel and environmentally friendly production method that provides omega-hydroxylated fatty acid derivatives at high purity and yield. Further encompassed are recombinant microorganisms that produce omega-hydroxylated fatty acid derivatives through selective fermentation.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: July 14, 2020
    Assignee: GENOMATICA, INC.
    Inventors: Andreas W. Schirmer, Haibo Wang, Stephen B. Del Cardayre, Zhihao Hu, Louis G. Hom, Baolong Zhu, Cindy Chang, Emanuela E. Popova
  • Publication number: 20200208414
    Abstract: The present disclosure provides an anti-slip floor tile including a base layer, a decorative layer on the base layer, and a wear resistant layer on the decorative layer. The wear resistant layer includes a non-rigid or semi-rigid thermoplastic resin, and a plurality of first mineral particles uniformly distributed inside the thermoplastic resin. The present disclosure can improve the wear resistance of the anti-slip floor tile by dispersing the first mineral particles in the wear resistant layer.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 2, 2020
    Inventors: HSIUNG-TIEH YU, STEPHEN CHANG
  • Publication number: 20200212198
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Application
    Filed: January 18, 2020
    Publication date: July 2, 2020
    Inventors: Steven R.J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Publication number: 20200203503
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Application
    Filed: January 21, 2020
    Publication date: June 25, 2020
    Inventors: Steven R.J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Publication number: 20200203316
    Abstract: Aspects of the disclosure relate to forming stacked NAND with multiple memory sections. Forming the stacked NAND with multiple memory sections may include forming a first memory section on a sacrificial substrate. A logic section may be formed on a substrate. The logic section may be bonded to the first memory section. The sacrificial substrate may be removed from the first memory section and a second memory section having a second sacrificial substrate may be formed and bonded to the first memory section.
    Type: Application
    Filed: July 26, 2019
    Publication date: June 25, 2020
    Applicant: Xcelsis Corporation
    Inventors: Stephen Morein, Javier A. Delacruz, Xu Chang, Belgacem Haba, Rajesh Katkar
  • Publication number: 20200202733
    Abstract: Systems, methods, and computer-readable media storing instructions for determining cross-track error of an aircraft on a taxiway are disclosed herein. The disclosed techniques capture electronic images of a portion of the taxiway using cameras or other electronic imaging devices mounted on the aircraft, pre-process the electronic images to generate regularized image data, apply a trained multichannel neural network model to the regularized image data to generate a preliminary estimate of cross-track error relative to the centerline of the taxiway, and post-process the preliminary estimate to generate an estimate of cross-track error of the aircraft. Further embodiments adjust a GPS-based location estimate of the aircraft using the estimate of cross-track error or adjust the heading of the aircraft based upon the estimate of cross-track error.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Tyler C. Staudinger, Kevin S. Callahan, Isaac Chang, Stephen Dame, Nick Evans, Zachary Jorgensen, Joshua Kalin, Eric Muir
  • Publication number: 20200203505
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Application
    Filed: January 21, 2020
    Publication date: June 25, 2020
    Inventors: Steven R.J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Publication number: 20200203504
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Application
    Filed: January 21, 2020
    Publication date: June 25, 2020
    Inventors: Steven R.J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Publication number: 20200161449
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Inventors: Steven R.J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Publication number: 20200161448
    Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Inventors: Steven R.J. Brueck, Stephen D. Hersee, Seung-Chang Lee, Daniel Feezell
  • Patent number: 10636871
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani, Titash Rakshit, Peter Chang, Willy Rachmady
  • Patent number: 10608075
    Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bhaskar Srinivasan, Guru Mathur, Stephen Arlon Meisner, Shih Chang Chang, Corinne Ann Gagnet
  • Patent number: 10598656
    Abstract: Lateral flow devices and methods of use for a molecular diagnostic assay are provided. The method is suitable for detection or monitoring of targets, including biological, chemical, and material targets that exist in very low concentrations in biological samples. The methods and devices of the present application are amenable to power source-free point of care testing.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 24, 2020
    Assignee: CREDO BIOMEDICAL PTE LTD.
    Inventors: Winston Wong, Jr., Stephen Chang-Chi Kao
  • Publication number: 20200084967
    Abstract: A grain tailings elevator for a combine harvester includes a an elevator housing having an interior containing a conveyor arrangement configured to transport grain tailings through the elevator housing to a discharge outlet. The elevator housing has a side wall with a window to the interior of the elevator housing. A camera having a camera housing containing an image sensor is mounted to the side wall of the elevator housing over the window with the image sensor in registration with the window. The image sensor is trained on the conveyor arrangement and configured to image the grain tailings transported by the conveyor arrangement through the elevator housing.
    Type: Application
    Filed: August 14, 2019
    Publication date: March 19, 2020
    Inventors: Stephen R. Corban, Scott Miller, William D. Todd, Herman Herman, Zachary Pezzementi, Trenton Tabor, Jonathan Chang
  • Publication number: 20200084966
    Abstract: A method and system for controlling the quality of harvested grains include capturing, by one or more image sensors, one or more images of material at a sampling location within a grain elevator of the combine harvester. The captured images are defined by a set of image pixels represented by image data and having a classification feature indicative of grain or non-grain material. One or more controllers receive the image data associated with the one or more images captured by the image sensor(s) and select a sample image defined by a subset of image pixels of the set of image pixels. The controller(s) apply a convolutional neural network (CNN) algorithm to the image data of the subset of image pixels of the selected sample image to determine the classification feature. The controller(s) analyze the determined classification feature to adjust an operational parameter of the combine harvester.
    Type: Application
    Filed: August 14, 2019
    Publication date: March 19, 2020
    Inventors: Stephen R. Corban, Scott Miller, Herman Herman, Zachary Pezzementi, Trenton Tabor, Jonathan Chang
  • Patent number: 10571714
    Abstract: An embodiment includes a snap-fit temple interface of a lens. The snap-fit temple interface includes a first snap-fit feature and a second snap-fit feature. The first snap-fit feature of the lens is configured to be engaged with a first corresponding snap-fit feature of a temple assembly. The first snap-fit feature is configured to be engaged with the first corresponding snap-fit feature by a first movement of the lens in a first direction relative to the temple assembly followed by a second movement of the lens in a second direction relative to the temple assembly. The second snap-fit feature of the lens is configured to be engaged with a second corresponding snap-fit feature of the temple assembly. The second snap-fit feature is configured to be engaged with the second snap-fit feature by the second movement of the lens in the second direction relative to the temple assembly. The first direction is substantially perpendicular to the second direction.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 25, 2020
    Assignee: Advanced Eye Protection IP Holding
    Inventors: Stephen Charles Chen, Chen Chang Wang Lee, Zong-Lin Du
  • Publication number: 20200038240
    Abstract: A comfortable insert comprises a retention structure sized for placement under the eyelids and along at least a portion of conjunctival sac of the upper and lower lids of the eye. The retention structure resists deflection when placed in the conjunctival sac of the eye and to guide the insert along the sac when the eye moves. The retention structure can be configured in many ways to provide the resistance to deflection and may comprise a hoop strength so as to urge the retention structure outward and inhibit movement of the retention structure toward the cornea. The insert may move rotationally with deflection along the conjunctival sac, and may comprise a retention structure having a cross sectional dimension sized to fit within folds of the conjunctiva. The insert may comprise a release mechanism and therapeutic agent to release therapeutic amounts of the therapeutic agent for an extended time.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Eugene de Juan, Jr., Yair Alster, Cary J. Reich, K. Angela Macfarlane, Janelle Chang, Stephen Boyd, David Sierra, Jose D. Alejandro, Douglas Sutton, Alexander J. Gould
  • Publication number: 20200032217
    Abstract: The present invention provides various improved systems and methods for obtaining, generating, culturing, and handling cells, such as stem cells (including induced pluripotent stem cells or iPSCs) and differentiated cells, as well as cells and cell panels produced using such systems and methods, and uses of such cells and cell panels.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 30, 2020
    Inventors: Scott Noggle, Kevin Eggan, Stephen Chang, Susan Solomon
  • Patent number: 10510436
    Abstract: The present invention discloses a method of real-time quantification of a target nucleic acid in a sample by constructing a reference table of copy number vs. designated parameter from reference samples which sharing the same nucleic acid sequences with the target nucleic acid. The method includes (a) constructing a reference table of copy number vs. designated parameter from reference samples; (b) amplifying the target nucleic acid; (c) monitoring and detecting the amplification of the target nucleic acid in real-time; (d) analyzing the detected signals to get the designated parameter of the target nucleic acid; and (e) looking up and interpolating to the reference table to get the copy number of the target nucleic acid.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: December 17, 2019
    Assignee: Credo Biomedical Pte Ltd.
    Inventors: Jr. Winston Wong, Stephen Chang-Chi Kao, Ying-Ta Lai, Yih-Jyh Shann, Ming-Fa Chen, Chih-Rong Chen