Abstract: Image processing apparatus comprises a demosaic processor for receiving a video signal comprising pixel data from an array of photosensors each having a respective color filter so as to restrict the sensitivity of that photosensor to a primary color range selected from a set of three or more primary color ranges, the array being such that the photosensors in alternate rows are sensitive to a first primary color range, and photosensors in intervening rows are sensitive to the other primary color ranges. The pixel data including pixel data from a first subset of the rows sensitive to the first primary color range, the first subset being the same from image to image of the video signal; and pixel data from a second subset of the rows of photosensors sensitive to the other primary color ranges, the second subset changing from image to image of the video signal.

Abstract: Image processing apparatus comprises a demosaic processor for receiving a video signal comprising pixel data from an array of photosensors each having a respective color filter so as to restrict the sensitivity of that photosensor to a primary color range selected from a set of three or more primary color ranges, the array being such that the photosensors in alternate rows are sensitive to a first primary color range, and photosensors in intervening rows are sensitive to the other primary color ranges. The pixel data including pixel data from a first subset of the rows sensitive to the first primary color range, the first subset being the same from image to image of the video signal; and pixel data from a second subset of the rows of photosensors sensitive to the other primary color ranges, the second subset changing from image to image of the video signal.

Abstract: The frequency of a local clock of a local data processor in communication with an asynchronous switched packet network is synchronized to the frequency of a reference clock of a source data processor also coupled to the network. Timing packets each including a field containing the destination address of the local processor and a field containing reference clock data indicating the time at which the packet is launched onto the network are sent to the local data processor from the source data processor across the network. The frequency of the local clock is controlled in dependence on the reference clock data and the times of arrival of the packets.

Abstract: A digital signal comprises data blocks. Each data block includes a header containing data relating to the block and a plurality of slots. Each slot has a slot header relating to the slot and a data packet. A plurality of data packets contains at least a first part and subsequent parts of the digital signal. A first slot includes the first part of the digital signal and a reference time defining a time of production of the first part. Each subsequent slot contains a subsequent part of the digital signal and timing information defining a time of production of the subsequent part relative to the reference time.

Abstract: An encoding apparatus operable to encode video data representing successive images, each image comprising a plurality of pixels, comprises a differential encoder arranged to encode each image as one or more predetermined image regions, each image region being encoded as a reference value and at least one differential pixel value, the differential pixel value(s) being derived in dependence on the reference value and/or other differential pixel value(s) in accordance with an order of encoding dependency; in which, for each image region, the differential encoder is operable in a first encoding mode for a first subset of the images to encode the image region using a first order of encoding dependency and in a second encoding mode for a second, different, subset of the images to encode the image region using a second, different, order of encoding dependency, and in which the first and second subsets of images are arranged with respect to one another so that, from image to image, each image region is encoded in acc

Abstract: The frequency of a local clock of a local data processor in communication with an asynchronous switched packet network is synchronized to the frequency of a reference clock of a source data processor also coupled to the network. Timing packets each including a field containing the destination address of the local processor and a field containing reference clock data indicating the time at which the packet is launched onto the network are sent to the local data processor from the source data processor across the network. The frequency of the local clock is controlled in dependence on the reference clock data and the times of arrival of the packets.

Abstract: A buffer (4) has a read and write control (8, 7), an input (6), an output (5), and a transfer port (9). An SCSI interface (20) is coupled to port (9) and the read/write control (8, 7). The SCSI interface (20) implements transfer commands for transfers via the port 9 with an undefined delay. An RS 422 interface is coupled to the read/write control (8) and implements transfer commands for transfers via the input 6 and output 5, the commands being implemented with a small, defined delay synchronously with a video sync signal (SYNC).