Patents by Inventor Stephen Ciavaglia

Stephen Ciavaglia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6397306
    Abstract: “Per memory” atomic access for a distributed memory multiprocessor architecture is provided by marking bit masks for shared memories to indicate the access privileges of processors to the memories. A processor has access privileges to a shared memory if the bit mask retained for the memory is marked at a bit position reserved for the processor and does not have access privileges if the bit mask is not so marked. A bit mask is permitted to have only one mark at a given time to guarantee that access to each shared memory is atomic.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: May 28, 2002
    Assignee: Alcatel Internetworking, Inc.
    Inventors: Stephen Ciavaglia, Arthur L. Zaifman, Edward C. Szajner, Jr., Edward Spang
  • Publication number: 20010042179
    Abstract: “Per memory” atomic access for a distributed memory multiprocessor architecture is provided by marking bit masks for shared memories to indicate the access privileges of processors to the memories. A processor has access privileges to a shared memory if the bit mask retained for the memory is marked at a bit position reserved for the processor and does not have access privileges if the bit mask is not so marked. A bit mask is permitted to have only one mark at a given time to guarantee that access to each shared memory is atomic.
    Type: Application
    Filed: October 23, 1998
    Publication date: November 15, 2001
    Inventors: STEPHEN CIAVAGLIA, ARTHUR L. ZAIFMAN, EDWARD C. SZAJNER JR., EDWARD SPANG
  • Patent number: 6292826
    Abstract: Shadow arrays are configured in a distributed memory multiprocessor architecture to localize memory referencing. As each additional processor becomes active a variable array having dimensions 1×N, including N single instance variables which must be monitored on a “per processor” basis, is configured in a memory local to the additional processor and made locally referenceable. A patchwork of shadow arrays is thereby established in which each additional processor may reference local memory to access its own value set for the N single instance variables. The single instance formatting of the arrays also advantageously facilitates migration from an single processor operating system to a multiprocessor operating system without substantial recoding.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: September 18, 2001
    Assignee: Alcatel Internetworking, Inc.
    Inventors: Arthur L. Zaifman, Stephen Ciavaglia, Edward C. Szajner, Jr.