Patents by Inventor Stephen D. Arthur

Stephen D. Arthur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7482634
    Abstract: The present invention is directed towards a source of ultraviolet energy, wherein the source is a UV-emitting LED's. In an embodiment of the invention, the UV-LED's are characterized by a base layer material including a substrate, a p-doped semiconductor material, a multiple quantum well, a n-doped semiconductor material, upon which base material a p-type metal resides and wherein the base structure has a mesa configuration, which mesa configuration may be rounded on a boundary surface, or which may be non-rounded, such as a mesa having an upper boundary surface that is flat. In other words, the p-type metal resides upon a mesa formed out of the base structure materials. In a more specific embodiment, the UV-LED structure includes n-type metallization layer, passivation layers, and bond pads positioned at appropriate locations of the device. In a more specific embodiment, the p-type metal layer is encapsulated in the encapsulating layer.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: January 27, 2009
    Assignee: Lockheed Martin Corporation
    Inventors: Robert John Wojnarowski, Stanton Earl Weaver, Jr., Abasifreke Udo Ebong, Xian An (Andrew) Cao, Steven Francis LeBoeuf, Larry Burton Rowland, Stephen D. Arthur
  • Patent number: 7002156
    Abstract: A detection system for detecting gamma rays including a scintillator crystal for receiving at least one gamma ray and generating at least one ultraviolet ray and an avalanche photodiode for detecting the ultraviolet ray. The avalanche photodiode includes: a substrate having a first dopant; a first layer having a second dopant, positioned on top of the substrate; a passivation layer for providing electrical passivation on a surface of the avalanche photodiode; a phosphorous silicate glass layer for limiting mobile ion transport, positioned above of the first layer; and a pair of metal electrodes for providing an ohmic contact wherein a first electrode is positioned below the substrate and a second electrode is positioned above the first layer. The avalanche photodiode comprises a first sidewall and a second sidewall forming a sloped mesa shape.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: February 21, 2006
    Assignee: General Electric Company
    Inventors: Peter M. Sandvik, Dale M. Brown, Stephen D. Arthur, Kevin S. Matocha, James W. Kretchmer
  • Patent number: 6838741
    Abstract: An aspect of the present invention is directed to an avalanche photodiode (APD) device for use in oil well drilling applications in harsh, down-hole environments where shock levels are near 250 gravitational acceleration (G) and/or temperatures approach or exceed 150° C. Another aspect of the present invention is directed to an APD device fabricated using SiC materials. Another aspect of the present invention is directed to an APD device fabricated using GaN materials.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: January 4, 2005
    Assignee: General Electtric Company
    Inventors: Peter M. Sandvik, Dale M. Brown, Stephen D. Arthur, Kevin S. Matocha, James W. Kretchmer
  • Publication number: 20040108530
    Abstract: An aspect of the present invention is directed to an avalanche photodiode (APD) device for use in oil well drilling applications in harsh, down-hole environments where shock levels are near 250 gravitational acceleration (G) and/or temperatures approach or exceed 150° C. Another aspect of the present invention is directed to an APD device fabricated using SiC materials. Another aspect of the present invention is directed to an APD device fabricated using GaN materials.
    Type: Application
    Filed: December 10, 2002
    Publication date: June 10, 2004
    Applicant: General Electric Company
    Inventors: Peter M. Sandvik, Dale M. Brown, Stephen D. Arthur, Kevin S. Matocha, James W. Kretchmer
  • Patent number: 5880513
    Abstract: An asymmetric snubber resistor in accordance with the present invention includes a cathode, an N+ region, an N- region, a plurality of P+ regions, and an anode. The N+ region is disposed over the cathode, the N- region is disposed over the N+ region, the plurality of P+ regions are disposed over the N- region, and the anode is disposed over the plurality of P+ regions and exposed portions of the N- region. The asymmetric snubber may also include N regions between the P+ regions. The asymmetric snubber resistor replaces the snubber diode and the snubber resistor in a typical snubber circuit.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: March 9, 1999
    Assignee: Harris Corporation
    Inventors: Victor A.K. Temple, Stephen D. Arthur, Sabih Al-Marayati, Eric X. Yang
  • Patent number: 5424563
    Abstract: The sensitivity of breakdown voltage to temperature and dV/dT induced currents is reduced in semiconductor power devices having a wide base transistor. The sensitivity is reduced by diverting current from the emitter of the wide base transistor to the base of the wide base transistor (an emitter short that does not reduce breakdown voltage) or by injecting a current into the base of the wide base transistor to its collector (an injected current that may lower the breakdown voltage, but no more than that related to temperature and capacitive current). The invention finds application in both epitaxial grown and substrate based devices.
    Type: Grant
    Filed: December 27, 1993
    Date of Patent: June 13, 1995
    Assignee: Harris Corporation
    Inventors: Victor A. K. Temple, Stephen D. Arthur, Donald L. Watrous, John M. S. Neilson
  • Patent number: 5041896
    Abstract: An improved symmetrical blocking high voltage semiconductor device structure incorporating a sinker region and a buried region adjacent the periphery of the chip improves device operating characteristics and simplifies device fabrication processes. A heavily doped polycrystalline refill of a trench provides a deep junction sidewall region which brings the lower high voltage blocking junction to the upper surface.
    Type: Grant
    Filed: July 6, 1989
    Date of Patent: August 20, 1991
    Assignee: General Electric Company
    Inventors: Victor A. K. Temple, Stephen D. Arthur, Peter V. Gray
  • Patent number: 4939101
    Abstract: Wafers which are direct bonded to each other in accordance with prior art processes suffer from voids at their bonded interface. Annealing such composite structures at high temperature and high pressure (for silicon wafers preferably about 1,100.degree. C. and 15,000 psi) eliminates all voids which are not a result of the presence of a particle on one of the wafers at the time of mating.
    Type: Grant
    Filed: September 6, 1988
    Date of Patent: July 3, 1990
    Assignee: General Electric Company
    Inventors: Robert D. Black, Stephen D. Arthur, Robert S. Gilmore, Homer H. Glascock, II
  • Patent number: 4927772
    Abstract: A semiconductor device having at least one P-N junction and a multiple-zone junction termination extension (JTE) region which uniformly merges with the reverse blocking junction is disclosed. The blocking junction is graded into multiple zones of lower concentration dopant adjacent termination to facilitate merging of the JTE to the blocking junction and placing of the JTE at or near the high field point of the blocking junction. Preferably, the JTE region substantially overlaps the graded blocking junction region. A novel device fabrication method is also provided which eliminates the prior art step of separately diffusing the JTE region.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: May 22, 1990
    Assignee: General Electric Company
    Inventors: Stephen D. Arthur, Victor A. K. Temple
  • Patent number: 4814283
    Abstract: A method for the discretionary interconnection of plural devices into an array includes the steps of designing bridge sites between the devices, individually testing the devices, inking over the bridge sites to devices which do not meet predetermined parameters, and soldering in a manner to cause the solder to bridge the gap between the acceptable devices and the rest of the array but not to bridge the gap to unacceptable devices. In devices comprised of multiple parallel elements, only sub-elements which fall within predetermined functional requirement ranges are incorporated into the parallel array produced. This method of discretionary interconnection is readily adapted to automated techniques for fabricating semiconductor MOS devices such as MCTs, IGBTs and parallel MOSFET arrays.
    Type: Grant
    Filed: April 8, 1988
    Date of Patent: March 21, 1989
    Assignee: General Electric Company
    Inventors: Victor A. K. Temple, Stephen D. Arthur