Abstract: To decrease the likelihood of a false detection when detecting light from light pulses scattered by remote targets in a lidar system, a receiver in the lidar system includes a photodetector and a pulse-detection circuit having a gain circuit with a varying amount of gain over time. The gain circuit operates in a low-gain mode for a time period T1 beginning with time t0 when a light pulse is emitted to prevent the receiver from detecting return light pulses during the threshold time period T1. Upon expiration of the threshold time period T1, the gain circuit operates in a high-gain mode to begin detecting return light pulses until a subsequent light pulse is emitted.

Abstract: A lidar system includes a light source configured to emit light pulses and a receiver configured to detect light from some of the light pulses scattered by remote targets. The receiver includes an avalanche photodiode operating in the linear mode for detecting the light pulses. To prevent damage to the linear mode avalanche photodiode a quench circuit is coupled to the avalanche photodiode, where the quench circuit reduces a bias voltage applied to the avalanche photodiode, when an avalanche event occurs at the avalanche photodiode.

Abstract: Read-out cell systems are disclosed for image detectors, including infrared image detectors, that provide improved sensitivity by providing in-cell subtraction through the use of a voltage ramp signal generated using a reference pixel and a feedback amplifier. The ramp voltage is generated using a reference pixel and an amplifier having feedback. The ramp voltage is then provided to a plurality of read-out cells. The ramp voltage can be coupled to an input transistor to provide current subtraction prior to the integration node. The ramp voltage can also be provided to integration capacitors within the read-out cells to provide current subtraction directly to the integration node. Further, a temperature-independent fixed current source can also be utilized to further control current subtraction.

Abstract: Read-out cell systems are disclosed for image detectors, including infrared image detectors, that provide improved sensitivity by providing in-cell subtraction through the use of a voltage ramp signal generated using a reference pixel and a feedback amplifier. The ramp voltage is generated using a reference pixel and an amplifier having feedback. The ramp voltage is then provided to a plurality of read-out cells. The ramp voltage can be coupled to an input transistor to provide current subtraction prior to the integration node. The ramp voltage can also be provided to integration capacitors within the read-out cells to provide current subtraction directly to the integration node. Further, a temperature-independent fixed current source can also be utilized to further control current subtraction.

Abstract: An integrating capacitor circuit for an integrating amplifier and related methods are disclosed that allow for efficient detection of currents or charges, particularly those produced by pixel cells in a detector image array. By placing a capacitor-connected field-effect-transistor (FET) in parallel with an integration capacitor and setting its gate voltage to a selected voltage level, the current or charge from the detector depletes the charge on the gate of the FET capacitor while integrating on the capacitor. In addition, the gate voltage level can be adjusted to modify the current depleting characteristics of the capacitor-connected FET. The resulting operation of this integrating circuitry provides significant resulting advantages for the integrating amplifier.

Abstract: An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combiner for adding the third and sixth charge packets and the fourth and fifth charge packets.

Abstract: An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combinet for adding the third and sixth charge packets and the fourth and fifth charge packets.

Abstract: An active matrix liquid crystal display includes an arrangement for maintaining the liquid crystal material of the display at a controlled temperature above ambient temperature. The liquid crystal material of the display is disposed over a substrate containing integrated circuitry. The arrangement for maintaining the temperature of the liquid crystal includes (i) an arrangement for heating the liquid crystal material sufficient to maintain the liquid crystal material at the controlled temperature, (ii) an arrangement for sensing the temperature at a location in close proximity to the liquid crystal material and producing an output signal representative of the temperature, and (iii) a servo-circuit responsive to the output signal for causing the heating arrangement to maintain the liquid crystal material at the controlled temperature.

Abstract: An improved CCD imaging array is disclosed which is capable of operating at 10,000 frames-per-second. The imager consists of an array of 512.times.512 pixels having 16 serial output channels which provides a composite output data rate up to 250 Megasamples/second. The serial output registers are constructed from peristaltic CCDs, each having a GaAs FET output circuit bump-mounted to the silicon substrate. A four-layer pinned photodiode is utilized as the photodetector, and each photodiode has its own antiblooming drain. The antiblooming gates double as an optical shuttering device. Sample-and-hold output circuitry is also provided.

Abstract: There is disclosed herein a liquid crystal spatial light modulator which is driven y an analog input voltage and which includes, among other components, a layer of liquid crystal material that changes the way in which it acts on light in response to predetermined changes in voltage across the layer, whereby to modulate the light so acted upon, and an arrangement for applying a light modulating voltage across the layer of liquid crystal material and for modulating the voltage during a given modulation period. This latter arrangement includes a non-linear capacitor and a voltage coupling scheme for changing the voltage across the capacitor during the modulation period in a way which changes the capacitance of the capacitor and thereby capacitively couples at least a part of the change in voltage across the capacitor to the layer of liquid crystal material.

Abstract: There is disclosed herein a liquid crystal spatial light modulator which includes, among other components, a layer of liquid crystal material which changes the way in which it acts on light in response to predetermined changes in voltage across the layer, whereby to modulate the light so acted upon, and an arrangement for applying a light modulating voltage across the layer of liquid crystal material and for modulating the voltage during a given modulation period. This latter arrangement includes a non-linear capacitor and a voltage coupling scheme for changing the voltage across the capacitor during the modulation period in a way which changes the capacitance of the capacitor and thereby capacitively couples at least a part of the change in voltage across the capacitor to the layer of liquid crystal material.

Abstract: A symmetric pipelined charge-mode analog to digital converter including a signal-reference CCD channel having a plurality of charge storage stages that are arranged in a serial configuration to carry the signal and reference charges, and a CCD digital channel. A set of two step comparators coupled to the signal-reference channel first senses and stores the signal charge and then senses and compares the reference charge to the signal charge. In the first stage, an initial reference charge is used, and in subsequent stages, an increment of one half the previous stage increment is added to the reference. In addition, at each stage, a charge increment equal to the previous reference increment is conditionally added to the signal charge and a corresponding bit in the digital channel is conditionally set responsive to the comparator.

Abstract: A symmetric pipelined charge-mode analog to digital converter including a signal-reference CCD channel having a plurality of charge storage stages that are arranged in a serial configuration to carry the signal and reference charges, and a CCD digital channel. A set of two step comparators coupled to the signal-reference channel first senses and stores the signal charge and then senses and compares the reference charge to the signal charge. In the first stage, an initial reference charge is used, and in subsequeant stages, an increment of one half the previous stage increment is added to the reference. In addition, at each stage, a charge increment equal to the previous reference increment is conditionally added to the signal charge and a corresponding bit in the digital channel is conditionally set responsive to the comparator.

Abstract: A floating point analog to digital converter having an exponent converter which divides the input signal successively one-half until the divided signal is within the range of a mantissa linear analog to digital converter. The exponent converter also generate a digital exponent representative of the division factor. The resulting divided signal is then digitized by the mantissa analog to digital converter. An output is thereby provided composed of a digital exponent and a digital mantissa. In one embodiment, the floating point converter is a charge mode converter suitable for direct interface to a charge mode device such as a CCD image sensor.

Abstract: An infrared detector has its sensor chip assembly (10,12,14) cooled to a relatively low temperature required for its operation, whereas a preamplifier (56) required to be positioned close to the sensor chip assembly and which generates considerably more heat than does the sensor chip assembly, is thermally isolated from the sensor chip assembly and its support (16) and is cooled to a higher temperature to thereby significantly reduce the power dissipated to the coldest refrigerator stage (90).

Abstract: A rear illuminated radiation detector comprising a rear contact adjacent to a substrate substantially transparent to incident radiation of a given frequency range, detector and blocking layers overlying said rear contact, and a front contact overlying the detector and blocking layers. The layers are disposed so that, through them, the front contact is in electrical contact with the rear contact. Radiation may enter the detector layer from the rear, through the substrate, thereby permitting the detector to be operated in a backside illuminated mode. Such detectors may be fabricated in highly dense arrays and coupled to either hybrid or monolithic readout structures as required for operation as a focal plane array radiation detector. Optionally, the front contact may be left exposed so that radiation may enter the detector layer from the front of the radiation detector, thereby permitting it to be operated in both backside and frontside illuminated modes.