Abstract: A transmitter for a high speed serial communications link, a serial communications link, and a receiver for a high speed serial communications link are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium having multiple lanes, and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode, wherein in the safe mode at least one of the lanes is dedicated to transmitting a link detect signal for link detection.

Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

Abstract: A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.

Abstract: A transmitter for a high speed serial communications link, a serial communications link, and a receiver for a high speed serial communications link are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium having multiple lanes, and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode, wherein in the safe mode at least one of the lanes is dedicated to transmitting a link detect signal for link detection.

Abstract: A transmitter for a serial communications link, a serial communications link and an electronic system are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode.

Abstract: A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.

Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

Abstract: A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.

Abstract: A transmitter for a serial communications link, a serial communications link and an electronic system are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode.

Abstract: A receiver, transmitter and method for enabling a replay using a packetized link protocol are provided. In one embodiment, the method includes: (1) transmitting a stream of packets including an untagged packet and (2) using synchronized counters to determine a sequence ID of the untagged packet, which is a corrupt/lost packet that needs to be retransmitted.

Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

Abstract: An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.

Abstract: A tunnel for a communication system includes first and second bridges. The first bridge has a first port adapted to couple to a first link and a second port, and has a first programmable bus number and a first programmable function number. The second bridge has a first port coupled to the second port of the first bridge, and a second port, and has a second programmable bus number and a second programmable function number. In a hoist enabled mode, the first bridge forwards a packet on the first link to the second bridge if the second programmable bus number is equal to the first programmable bus number, a bus number of the packet is equal to the first programmable bus number, and a function number of the packet is equal to the second programmable function number.

Abstract: An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache line. The apparatus further comprises an atomic program execution unit that is configured to execute the atomic program as a single atomic memory transaction with a guarantee of forward progress.

Abstract: A bus protocol compatible requester includes a bus protocol port for transmitting bus protocol compatible requests to a bus protocol link, and an extended atomic operation generation system, coupled to the bus protocol port, for generating an extended atomic operation by using at least one bit in a field of a standard bus protocol request other than an opcode field, and providing the extended atomic operation to the bus protocol port for transmission to a completer. A bus protocol compatible completer includes a bus protocol port for receiving bus protocol compatible requests from a bus protocol link, and an extended atomic operation execution system, coupled to the bus protocol port, for decoding an extended atomic operation according to at least one bit in a field of a standard bus protocol request other than an opcode field, and executing the extended atomic operation according to the at least one bit.

Abstract: A tunnel for a communication system includes first and second bridges. The first bridge has a first port adapted to couple to a first link and a second port, and has a first programmable bus number and a first programmable function number. The second bridge has a first port coupled to the second port of the first bridge, and a second port, and has a second programmable bus number and a second programmable function number. In a hoist enabled mode, the first bridge forwards a packet on the first link to the second bridge if the second programmable bus number is equal to the first programmable bus number, a bus number of the packet is equal to the first programmable bus number, and a function number of the packet is equal to the second programmable function number.

Abstract: Methods and apparatus are provided for implementing transaction layer processing (TLP) hint (TPH) protocols in the context of the peripheral component interconnect express (PCIe) base specification. The method allows an endpoint function associated with a PCI Express device to configure a steering tag header in the open systems interconnect (OSI) transaction layer to identify a particular processing resource that the requester desires to target, such as a specific processor or cache location within the execution core. A bit mask may be implemented by the hardware or operating system, for example, by embedding the bit mask in the steering tag header. The bit mask provides administrative oversight of the steering tag header configuration, to thereby mitigate unintended denial of service attacks or cache misses occasioned by aggressive steering tag configuration strategies employed by endpoint functions.

Abstract: Methods and apparatus are provided for implementing a lightweight notification (LN) protocol in the PCI Express base specification which allows an endpoint function associated with a PCI Express device to register interest in one or more cachelines in host memory, and to request an LN notification message from the CPU/memory complex when the content of a registered cacheline changes. The LN notification message can be unicast to a single endpoint using ID-based routing, or broadcast to all devices on a given root port. The LN protocol may be implemented in the CPU complex by configuring a queue or other data structure in system memory for LN use. An endpoint registers a notification request by setting the LN bit in a “read” request of an LN configured cacheline.

Abstract: An apparatus, method, and medium are disclosed for managing memory access from I/O devices. The apparatus comprises a memory management unit configured to receive, from an I/O device, a request to perform a memory access operation to a system memory location. The memory management unit is configured to detect that the request omits a memory access parameter, determine a value for the omitted parameter, and cause the memory access to be performed using the determined value.