Patents by Inventor Stephen D. Presant
Stephen D. Presant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240069616Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.Type: ApplicationFiled: September 6, 2023Publication date: February 29, 2024Inventors: OLEKSANDR KHODORKOVSKY, STEPHEN D. PRESANT
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Patent number: 11782494Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.Type: GrantFiled: September 4, 2018Date of Patent: October 10, 2023Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Oleksandr Khodorkovsky, Stephen D. Presant
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Publication number: 20180373306Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.Type: ApplicationFiled: September 4, 2018Publication date: December 27, 2018Inventors: OLEKSANDR KHODORKOVSKY, STEPHEN D. PRESANT
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Patent number: 10095295Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.Type: GrantFiled: December 14, 2011Date of Patent: October 9, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Oleksandr Khodorkovsky, Stephen D. Presant
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Publication number: 20160180487Abstract: A GPU of a processor performers load balancing by enabling and disabling CUs based on the GPU's processing load. A power control module identifies a current processing load of the GPU based on, for example, an activity level of one or more modules of the GPU. The power control module also identifies an expected future processing load of the GPU based on, for example, a number of threads (wavefronts) scheduled to be executed at the GPU. Based on a combination of the current processing load and the expected future processing load, the power control module sets the number of CUs of the GPU that are enabled and the number that are disabled (e.g. clock gated or power gated). By changing the number of enabled CUs based on processing load, the power control module maintains performance at the GPU while conserving power.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Dawid Trawczynski, Ken Correll, Stephen D. Presant, Tushar Shah, Ganesh Chandrasekaran, Rashad Oreifej
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Patent number: 9348656Abstract: A method and apparatus includes a multi-processor apparatus including a plurality of integrated circuit processors having a shared thermal platform. Each processor has at least one subsystem operable at a plurality of different power settings, at least one internal thermal parameter detector providing power data related to the processor, and a power management unit. The method and apparatus illustratively shares power data from the at least one internal thermal parameter detector of each processor between the power management units of the plurality of processors; compares the shared power data from the plurality of processors to a thermal design power limit for the shared thermal platform; and controls a power setting of the at least one subsystem of the plurality of processors within the shared thermal platform based on the comparison of the shared power data to the thermal design power limit for the shared thermal platform.Type: GrantFiled: December 19, 2011Date of Patent: May 24, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Stephen D. Presant, Alexander J. Branover, Oleksandr Khodorkovsky, Ljubisa Bajic
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Patent number: 8909961Abstract: Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency.Type: GrantFiled: November 29, 2011Date of Patent: December 9, 2014Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Jeffrey Herman, Krishna Sitaraman, Jia An Huang, Stephen D. Presant, Ali Ibrahim, Ashwini Dwarakanath
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Patent number: 8892919Abstract: A method and apparatus determines an activity history context for each of a plurality of virtual machines sharing use of a graphics processing core. Each activity history context provides information related to a power setting of at least one engine of the graphics processing core during at least one prior use of the graphics processing core by the corresponding virtual machine. The method and apparatus controls a power setting of the at least one engine of the graphics processing core based on the activity history context corresponding to an active virtual machine using the graphics processing core.Type: GrantFiled: December 14, 2011Date of Patent: November 18, 2014Assignee: ATI Technologies ULCInventors: Oleksandr Khodorkovsky, Stephen D. Presant
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Patent number: 8862924Abstract: Methods and apparatuses are provided for power control in a processor. The apparatus comprises a plurality of operational units arranged as a group of operational units. A power consumption monitor determines when cumulative power consumption of the group of operational units exceeds a threshold (e.g., either or both of the cumulative power threshold and the cumulative power rate threshold) during a time interval, after which a filter for issuing instructions to the group of operational units suspends instruction issuance to the group of operational units for the remainder of the time interval. The method comprises monitoring cumulative power consumption by a group of operational units within a processor over a time interval. If the cumulative power consumption of the group of operational units exceeds the threshold, instruction issuance to the group of operational units is suspended for the remainder of the time interval.Type: GrantFiled: November 15, 2011Date of Patent: October 14, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Brian D. Emberling, Stephen D. Presant, Seth Hendrickson, Krishna Sitaraman, Ali Ibrahim, Jeff Herman
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Publication number: 20130159755Abstract: A method and apparatus includes a multi-processor apparatus including a plurality of integrated circuit processors having a shared thermal platform. Each processor has at least one subsystem operable at a plurality of different power settings, at least one internal thermal parameter detector providing power data related to the processor, and a power management unit. The method and apparatus illustratively shares power data from the at least one internal thermal parameter detector of each processor between the power management units of the plurality of processors; compares the shared power data from the plurality of processors to a thermal design power limit for the shared thermal platform; and controls a power setting of the at least one subsystem of the plurality of processors within the shared thermal platform based on the comparison of the shared power data to the thermal design power limit for the shared thermal platform.Type: ApplicationFiled: December 19, 2011Publication date: June 20, 2013Applicants: Advanced Micro Devices, Inc., ATI Technologies, ULCInventors: Stephen D. Presant, Alexander J. Branover, Oleksandr Khodorkovsky, Ljubisa Bajic
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Publication number: 20130155045Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Applicants: Advanced Micro Devices, Inc., ATI Technologies, ULCInventors: Oleksandr Khodorkovsky, Stephen D. Presant
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Publication number: 20130155073Abstract: A method and apparatus determines an activity history context for each of a plurality of virtual machines sharing use of a graphics processing core. Each activity history context provides information related to a power setting of at least one engine of the graphics processing core during at least one prior use of the graphics processing core by the corresponding virtual machine. The method and apparatus controls a power setting of the at least one engine of the graphics processing core based on the activity history context corresponding to an active virtual machine using the graphics processing core.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Applicants: Advanced Micro Devices, Inc., ATI Technologies, ULCInventors: Oleksandr Khodorkovsky, Stephen D. Presant
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Publication number: 20130138977Abstract: Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency.Type: ApplicationFiled: November 29, 2011Publication date: May 30, 2013Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Jeffrey Herman, Krishna Sitaraman, Jia An Huang, Stephen D. Presant, Ali Ibrahim, Ashwini Dwarakanath
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Publication number: 20130124900Abstract: Methods and apparatuses are provided for power control in a processor. The apparatus comprises a plurality of operational units arranged as a group of operational units. A power consumption monitor determines when cumulative power consumption of the group of operational units exceeds a threshold (e.g., either or both of the cumulative power threshold and the cumulative power rate threshold) during a time interval, after which a filter for issuing instructions to the group of operational units suspends instruction issuance to the group of operational units for the remainder of the time interval. The method comprises monitoring cumulative power consumption by a group of operational units within a processor over a time interval. If the cumulative power consumption of the group of operational units exceeds the threshold, instruction issuance to the group of operational units is suspended for the remainder of the time interval.Type: ApplicationFiled: November 15, 2011Publication date: May 16, 2013Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Brian D. Emberling, Stephen D. Presant, Seth Hendrickson, Krishna Sitaraman, Ali Ibrahim, Jeff Herman
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Patent number: 4855899Abstract: A method of performing an input/output process containing a programmed input/output (PIO) instruction in a multiprocessor system including at least two processors each having an associated I/O bus with I/O devices connected thereto. The method has the steps of storing a unique address and a bus location for each I/O device in a device location table, determining the address of a referenced I/O device prior to performing the PIO instruction, reading the corresponding I/O bus location of the referenced I/O device from the device location table and executing the input/output process on the prescribed processor associated with the I/O bus to which the referenced I/O device is located. The method is used in conjunction with a task scheduler including a process control block for each scheduled process. When the PIO instruction references a device on the local I/O bus, the input/output process is executed normally.Type: GrantFiled: April 13, 1987Date of Patent: August 8, 1989Assignee: Prime Computer, Inc.Inventor: Stephen D. Presant