Abstract: A manufacturing process prioritization system. In one embodiment, the system includes at least one computing device adapted to prioritize a very large scale integration (VLSI) process, by performing actions including: querying a database for task-based data associated with a set of manufacturing tasks; applying at least one rule to the task-based data to prioritize a first one of the set of manufacturing tasks over a second one of the set of manufacturing tasks; and providing a set of processing instructions for processing a manufactured product according to the prioritization.

Abstract: A manufacturing process prioritization system. In one embodiment, the system includes at least one computing device adapted to prioritize a very large scale integration (VLSI) process, by performing actions including: querying a database for task-based data associated with a set of manufacturing tasks; applying at least one rule to the task-based data to prioritize a first one of the set of manufacturing tasks over a second one of the set of manufacturing tasks; and providing a set of processing instructions for processing a manufactured product according to the prioritization.

Abstract: A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Abstract: A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.

Abstract: A method, multi-computer media and apparatus that uses an economics model to manage the demand and the resource satisfying that demand for multi-computer memory. The present invention quantifies demand as a function of space, and computer resource as a function of time, so that a computational system can meet an application demand.

Abstract: Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.

Abstract: A method, multi-computer media and apparatus that uses an economics model to manage the demand and the resource satisfying that demand for multi-computer memory. The present invention quantifies demand as a function of space, and computer resource as a function of time, so that a computational system can meet an application demand.