Patents by Inventor Stephen D. Wyatt
Stephen D. Wyatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11099601Abstract: A calibration controller determines a latest arriving data strobe from at least one data chip at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller determines whether external feedback of the at least one data chip is required. The calibration controller, in response to determining that external feedback of the at least one data chip is required, aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe by applying a 180 degree phase align of the chip clock through one or more latches, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary.Type: GrantFiled: August 29, 2019Date of Patent: August 24, 2021Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt
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Patent number: 10698440Abstract: A calibration controller determines a latest arriving data strobe at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary. The calibration controller aligns the chip clock with a high speed clock for controlling an unload pointer to unload the data from the second data buffer to a serializer in the read data path, wherein the data cross a second clock boundary from the second data buffer to the serializer, to minimize a latency in the read data path across a second clock boundary.Type: GrantFiled: January 10, 2018Date of Patent: June 30, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt
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Publication number: 20190384352Abstract: A calibration controller determines a latest arriving data strobe from at least one data chip at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller determines whether external feedback of the at least one data chip is required. The calibration controller, in response to determining that external feedback of the at least one data chip is required, aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe by applying a 180 degree phase align of the chip clock through one or more latches, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt
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Publication number: 20190212769Abstract: A calibration controller determines a latest arriving data strobe at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe, wherein data crosses a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary. The calibration controller aligns the chip clock with a high speed clock for controlling an unload pointer to unload data from the second data buffer to a serializer in the read data path, wherein data crosses a second clock boundary from the second data buffer to the serializer, to minimize a latency in the read data path across a second clock boundary.Type: ApplicationFiled: January 10, 2018Publication date: July 11, 2019Inventors: Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt
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Patent number: 10162773Abstract: A system for memory management includes an incoming memory data strobe connecting a memory data interface, and a clock distribution network. The clock distribution network includes an internal clock aligned to the incoming memory data strobe. The system also includes an asynchronous clock domain that is asynchronous with the clock distribution network; and a strobe select circuit configured to align to the incoming memory data strobe. The clock distribution network is configured to propagate read data with reduced latency from the memory data interface to a second interface.Type: GrantFiled: November 15, 2017Date of Patent: December 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt
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Patent number: 8385394Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.Type: GrantFiled: February 2, 2012Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Brandon R. Kam, Stephen D. Wyatt
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Publication number: 20120134403Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.Type: ApplicationFiled: February 2, 2012Publication date: May 31, 2012Applicant: International Business Machines CorporationInventors: Brandon R. Kam, Stephen D. Wyatt
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Patent number: 8126041Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.Type: GrantFiled: October 19, 2007Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Brandon R. Kam, Stephen D. Wyatt
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Patent number: 8035452Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.Type: GrantFiled: March 28, 2008Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, John A. Fifield, Stephen D. Wyatt
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Patent number: 7932774Abstract: A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.Type: GrantFiled: March 24, 2008Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Anthony R. Bonaccio, Hayden C. Cranford, Jr., Joseph A. Iadanza, Sebastian T. Ventrone, Stephen D. Wyatt
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Patent number: 7755420Abstract: Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.Type: GrantFiled: August 22, 2008Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Anthony R. Bonaccio, Hayden C. Cranford, Jr., Joseph A. Iadanza, Sebastian T. Ventrone, Stephen D. Wyatt
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Patent number: 7710141Abstract: A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.Type: GrantFiled: January 2, 2008Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Giuseppe La Rosa, Kevin Kolvenbach, Ping-Chuan Wang, Stephen D. Wyatt
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Patent number: 7701270Abstract: Disclosed are design structures for current sink and source circuits, a charge pump, and a phase locked loop. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.Type: GrantFiled: August 27, 2007Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Stephen D. Wyatt, Tian Xia
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Publication number: 20090243733Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Inventors: Wagdi W. Abadeer, John A. Fifield, Stephen D. Wyatt
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Patent number: 7583116Abstract: Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.Type: GrantFiled: August 3, 2007Date of Patent: September 1, 2009Assignee: International Business Machines CorporationInventors: Stephen D. Wyatt, Tian Xia
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Publication number: 20090167336Abstract: A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.Type: ApplicationFiled: January 2, 2008Publication date: July 2, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giuseppe La Rosa, Kevin Kolvenbach, Ping-Chuan Wang, Stephen D. Wyatt
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Publication number: 20090102452Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.Type: ApplicationFiled: October 19, 2007Publication date: April 23, 2009Inventors: Brandon R. Kam, Stephen D. Wyatt
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Publication number: 20090051420Abstract: Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.Type: ApplicationFiled: August 22, 2008Publication date: February 26, 2009Applicant: International Business Machines CorporationInventors: Anthony R. Bonaccio, Hayden C. Cranford, JR., Joseph A. Iadanza, Sebastian T. Ventrone, Stephen D. Wyatt
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Publication number: 20090033383Abstract: Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.Type: ApplicationFiled: August 3, 2007Publication date: February 5, 2009Inventors: Stephen D. Wyatt, Tian Xia
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Publication number: 20090033407Abstract: Disclosed are design structures for current sink and source circuits, a charge pump, and a phase locked loop. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.Type: ApplicationFiled: August 27, 2007Publication date: February 5, 2009Inventors: Stephen D. Wyatt, Tian Xia