Abstract: Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive to their time domain variations at respective frequencies. A simulated, substantially noise-only, clock tree output signal is generated in a frequency domain, wherein some components are removed responsive to at least one clock signal frequency and scaled magnitudes of the components. A second simulated clock circuitry output signal is generated responsive to a transfer function of certain clock circuitry. A circuit structure or fabricating process is selected responsive to jitter of the second simulated clock circuitry output signal. The IC may be fabricated using the selected process and may include the selected structure.

Abstract: Designing integrated circuitry (“IC”) includes simulating noise of modeled IC operation and applying the noise to buffers of a clock tree of the modeled IC, responsively generating a first simulated clock tree output signal. Components of the first simulated clock tree output signal are scaled in a frequency domain responsive to their time domain variations at respective frequencies. A simulated, substantially noise-only, clock tree output signal is generated in a frequency domain, wherein some components are removed responsive to at least one clock signal frequency and scaled magnitudes of the components. A second simulated clock circuitry output signal is generated responsive to a transfer function of certain clock circuitry. A circuit structure or fabricating process is selected responsive to jitter of the second simulated clock circuitry output signal. The IC may be fabricated using the selected process and may include the selected structure.

Abstract: A network driver includes first and second driver circuits and a controller which controls the driver circuits. The first driver circuit is coupled to a first node, and the first driver circuit sources first and second discrete currents to the first node and sinks first and second discrete currents from the node. The second driver circuit is coupled to a second node, and the second driver circuit sources the first and second discrete currents to the second node and sinks the first and second discrete currents from the second node. The controller controls the driver circuits so that the first driver circuit sources and the second driver circuit sinks the first current followed by the second current and so that the first driver circuit sinks and the second driver circuit sources the first current followed by the second current. Related methods are also discussed.

Abstract: Jitter is controlled in a phase locked loop (PLL) adaptively and continuously in real time by a jitter control circuit. The jitter control circuit makes periodic PLL output jitter measurements and causes sequential measurements to be compared. The comparison provides an indication as to whether output jitter is being improved or degraded. Charge pump gains associated with internal parameters and external parameters that adversely affect output jitter are modified in response to the comparisons. If output jitter is adversely affected by an increment or decrement of one of the gain values, then the gain value is moved in the opposite direction. Output jitter is optimized for both gain values. Such optimization occurs during normal circuit operation and is continuous so as to adapt to changing conditions.

Abstract: A built-in system and method is provided that measures Phase Lock Loop (PLL) output clock error. An edge sorting circuit is utilized to measure jitter between corresponding transition edges of a measured clock and a reference clock, and then stores the value in an N bit word. A decoder circuit reads in the value and increments a corresponding counter. A state machine then reads the counters, processes the information and outputs one or more PLL clock error values.