Abstract: The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.

Abstract: The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.

Abstract: The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.

Abstract: All feedback cycles in a circuit network which cross only non-scannable memory elements are detected in linear run time. The method models a circuit network as a directed graph, then attributes network elements so that a single feedback cycle may be found in constant time. In the breadth first version, feedback is detected by traversing at most a constant distance back to the last scannable memory element. In the depth first version, graph nodes are not FINISHED until all predecessors are FINISHED. Feedback is found immediately if a node runs into another node that is NOT—FINISHED. This feedback is illegal if both nodes are in a zone defined by the same scannable memory element. The resulting identification and removal of feedback loops crossing only non-scannable memory elements significantly reduces the subsequent complexity of test pattern generation. This ensures a faster, more reliable, and more accurate test process after circuit fabrication.

Abstract: A method and structure for optimizing a solution for a complex problem typically solved by software tools includes selectively converting problem data into a format appropriate for one or more preselected vendor's set of solution tools and inputting the formatted design data into the one or more preselected vendor's set of solution tools. If more than one vendor has been preselected, resultant solution results are compared and the optimum solution is selected.

Abstract: All feedback cycles in a circuit network which cross only non-scannable memory elements are detected in linear run time. The method models a circuit network as a directed graph, then attributes network elements so that a single feedback cycle may be found in constant time. In the breadth first version, feedback is detected by traversing at most a constant distance back to the last scannable memory element. In the depth first version, graph nodes are not FINISHED until all predecessors are FINISHED. Feedback is found immediately if a node runs into another node that is NOT_FINISHED. This feedback is illegal if both nodes are in a zone defined by the same scannable memory element. The resulting identification and removal of feedback loops crossing only non-scannable memory elements significantly reduces the subsequent complexity of test pattern generation. This ensures a faster, more reliable, and more accurate test process after circuit fabrication.

Abstract: A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.

Abstract: A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

Abstract: The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.

Abstract: A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.

Abstract: A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.

Abstract: A method and structure for optimizing a solution for a complex problem typically solved by software tools includes selectively converting problem data into a format appropriate for one or more preselected vendor's set of solution tools and inputting the formatted design data into the one or more preselected vendor's set of solution tools. If more than one vendor has been preselected, resultant solution results are compared and the optimum solution is selected.

Abstract: Balanced-delay programmable logic array and a method for balancing programmable logic array delays provide improved performance in circuits employing programmable logic. By adding transistors to the programming plane that do not form part of the logic implementation, the capacitance on each of the input logic lines can be balanced, substantially reducing the skew between signals entering the final logic gates. This provides programmable logic arrays that may implement asynchronous logic in applications where skew was previously prohibitive and further increases the reliability of state evaluations in synchronous logic.