Patents by Inventor Stephen Dussinger

Stephen Dussinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250210591
    Abstract: An integrated circuit die includes a set of electronic circuits disposed on a semiconductor material. The integrated circuit die also includes one or more through-silicon vias that vertically span the semiconductor material to transmit data signals. Additionally, the integrated circuit die includes a programmable delay element integrated with the set of electronic circuits on the semiconductor material and configured to delay data signals. Various other apparatuses, systems, and methods are also disclosed.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Russell Schreiber, Stephen Dussinger, Eric Busta, Ryan J. Miller, John Wuu
  • Publication number: 20250210557
    Abstract: A bonded die assembly includes first conductive pads of a first substrate each bonded to respective second conductive pads of a second substrate, the first and second conductive pads arrayed at an inter-pad spacing, a plurality of active components located in the second substrate and arrayed at an inter-component spacing, and a metallization structure disposed between the first substrate and the second substrate, where the metallization structure is configured to decrease the inter-component spacing relative to the inter-pad spacing. The die assembly is characterized by an improved utilization of available device active area.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Darryl Prudich, Carson Donahue Henrion, Eric Busta, John Wuu, Russell Schreiber, Stephen Dussinger
  • Publication number: 20250210497
    Abstract: A method for controlling power in 3D stacked die can include configuring a first die of a set of 3D stacked die to receive power from a power source, wherein the first die includes one or more field effect transistors configured to control the power. The method can also include configuring one or more power domains included in a second die of the set of 3D stacked die to receive the power that is controlled by the one or more field effect transistors included in the first die. Various other methods and systems are also disclosed.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Stephen Dussinger, Richard Martin Born, Eric Busta, Carson Donahue Henrion, Jeffrey Lucas, Alistair Tomlinson, John Wuu
  • Publication number: 20250174985
    Abstract: An exemplary apparatus includes a through-silicon via (TSV) and circuit that protects against the antenna effect and electrostatic discharge (ESD). The circuit can include a plurality of transistors whose gates are each electrically coupled to a signal that passes through the TSV. Various other apparatuses, systems, and methods are also disclosed.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 29, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Stephen Dussinger, William E. Laub, JR., John Wuu