Patents by Inventor Stephen E. Jarboe

Stephen E. Jarboe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9600279
    Abstract: Search circuitry responsive to a single instruction for undertaking a step of a search of a data array for an extreme value therein, a method of searching a data array to identify an extreme value therein and a location thereof and a single-instruction, multiple-data (SIMD) processing unit incorporating the search circuitry or the method. In one embodiment, the search circuitry includes: a comparison element configured to compare two values in the data array, (2) multiplexers coupled to the comparison element and configured to select a more extreme value of the two values and a location in the data array of the more extreme value and (3) an incrementer configured to increment a counter associated with the search.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: March 21, 2017
    Assignee: VERISILICON HOLDINGS CO., LTD.
    Inventor: Stephen E. Jarboe
  • Publication number: 20140032879
    Abstract: Search circuitry responsive to a single instruction for undertaking a step of a search of a data array for an extreme value therein, a method of searching a data array to identify an extreme value therein and a location thereof and a single-instruction, multiple-data (SIMD) processing unit incorporating the search circuitry or the method. In one embodiment, the search circuitry includes: a comparison element configured to compare two values in the data array, (2) multiplexers coupled to the comparison element and configured to select a more extreme value of the two values and a location in the data array of the more extreme value and (3) an incrementer configured to increment a counter associated with the search.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: VeriSilicon Holdings Co., Ltd
    Inventor: Stephen E. Jarboe
  • Publication number: 20140032626
    Abstract: A multiply-accumulate unit (MAU) configurable to perform both real and complex multiplication operations, a method of performing a mac operation and a processing unit incorporating the MAU or the method. In one embodiment, the MAU includes: (1) a first multiplier having a first vector input and a first scalar input and configured to multiply a first vector by a first scalar to yield a first product, (2) a second multiplier having a second vector input and a second scalar input and configured to multiply a second vector by a second scalar to yield a second product and (3) an accumulator coupled to the first multiplier and the second multiplier and configured to receive the first and second products.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: VeriSilicon Holdings Co., Ltd.
    Inventor: Stephen E. Jarboe