Abstract: A server interconnect system includes a first server node operable to send and receive messages and a second server nodes operable to send and receive messages. The system further comprises a first interface unit in communication with the first server node and a second interface unit in communication with the second server node. The first interface unit has a first set of message send registers and a first set of message receive registers. Similarly, the second interface unit has a second set of message send registers and a second set of message receive registers. The server interconnect system also includes a communication switch that receives and routes a message from the first or second server nodes when either of the first or second registers indicates that a valid message is ready to be sent. A method implemented by the server interconnect system is also provided.

Abstract: A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.

Abstract: A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request.

Abstract: A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request.

Abstract: A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.

Abstract: A method and a system for processor nodes configurable to operate in various distributed shared memory topologies. The processor node may be coupled to a first local memory. The first processor node may include a first local arbiter, which may be configured to perform one or more of a memory node decode or a coherency check on the first local memory. The processor node may also include a switch coupled to the first local arbiter for enabling and/or disabling the first local arbiter. Thus one or more processor nodes may be coupled together in various distributed shared memory configurations, depending on the configuration of their respective switches.

Abstract: A system for automatic lane failover includes a first device coupled to a second device via a serial communication link having a plurality of a communication lanes. The devices may communicate by operating the link in a normal mode and a degraded mode. During normal mode operation, the devices may send frames of information to each other via the serial communication link. Each frame of information may include a number of data bits and a number of error protection bits. In response to either device detecting a failure of one or more of the communication lanes, the first device may cause the serial communication link to operate in a degraded mode by removing the one or more failed communication lanes. In addition, each device may reformat and send the frame of information on the remaining communication lanes with fewer data bits and the same number of error protection bits.

Abstract: A system for automatic lane failover includes a first device coupled to a second device via a serial communication link having a plurality of a communication lanes. The devices may communicate by operating the link in a normal mode and a degraded mode. During normal mode operation, the devices may send frames of information to each other via the serial communication link. Each frame of information may include a number of data bits and a number of error protection bits. In response to either device detecting a failure of one or more of the communication lanes, the first device may cause the serial communication link to operate in a degraded mode by removing the one or more failed communication lanes. In addition, each device may reformat and send the frame of information on the remaining communication lanes with fewer data bits and the same number of error protection bits.

Abstract: A method and a system for processor nodes configurable to operate in various distributed shared memory topologies. The processor node may be coupled to a first local memory. The first processor node may include a first local arbiter, which may be configured to perform one or more of a memory node decode or a coherency check on the first local memory. The processor node may also include a switch coupled to the first local arbiter for enabling and/or disabling the first local arbiter. Thus one or more processor nodes may be coupled together in various distributed shared memory configurations, depending on the configuration of their respective switches.

Abstract: In one embodiment, a node comprises at least one memory control unit configured to couple to an industry standard memory interface for coupling to a memory; and at least one coherence unit configured to transmit and receive coherence messages to and from other nodes to maintain coherent memory among the nodes. The coherence messages are conveyed on a second interface to which the coherence unit is coupled, wherein the second interface includes at least a physical layer as specified by the industry standard memory interface.

Abstract: A server interconnect system includes a first server node operable to send and receive messages and a second server nodes operable to send and receive messages. The system further comprises a first interface unit in communication with the first server node and a second interface unit in communication with the second server node. The first interface unit has a first set of message send registers and a first set of message receive registers. Similarly, the second interface unit has a second set of message send registers and a second set of message receive registers. The server interconnect system also includes a communication switch that receives and routes a message from the first or second server nodes when either of the first or second registers indicates that a valid message is ready to be sent. A method implemented by the server interconnect system is also provided.

Abstract: A server interconnect system for sending data includes a first server node and a second server node. Each server node is operable to send and receive data. The interconnect system also includes a first and second interface unit. The first interface unit is in communication with the first server node and has one or more RDMA doorbell registers. Similarly, the second interface unit is in communication with the second server node and has one or more RDMA doorbell registers. The system also includes a communication switch that is operable to receive and route data from the first or second server nodes using a RDMA read and/or an RDMA write when either of the first or second RDMA doorbell registers indicates that data is ready to be sent or received.

Abstract: In one embodiment, a node comprises a plurality of processor cores, coherency control circuitry coupled to the plurality of processor cores, and at least one coherence unit coupled to the coherency control circuitry. Each processor core is configured to have a plurality of threads active and each processor core includes at least one first level cache. The coherency control circuitry is configured to manage intranode coherency among the plurality of processor cores. The coherency unit is configured to couple to an external interface of the node, and is configured to transmit and receive coherence messages on the external interface to maintain coherency with at least one other node having one or processor cores and a coherence unit. In another embodiment, a system comprises an interconnect and a plurality of nodes coupled to the interconnect.

Abstract: In one embodiment, a node comprises at least one processor core and a plurality of coherence units. The processor core is configured to generate an address to access a memory location. The address maps to a first coherence plane of a plurality of coherence planes. Coherence activity is performed within each coherence plane independent of other coherence planes, and a mapping of the address space to the coherence planes is independent of a physical location of the addressed memory in a distributed system memory. Each coherence unit corresponds to a respective coherence plane and is configured to manage coherency for the node and for the respective coherence plane. The coherence units operate independent of each other, and a first coherence unit corresponding to the first coherence plane is coupled to receive the address if external coherency activity is needed to complete the access to the memory location.