Abstract: Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.

Abstract: A cache coherent multiple processor integrated circuit. The circuit includes a plurality of processor units. The processor units are each provided with a cache unit. An embedded RAM unit is included for storing instructions and data for the processor units. A cache coherent bus is coupled to the processor units and the embedded RAM unit. The bus is configured to provide cache coherent snooping commands to enable the processor units to ensure cache coherency between their respective cache units and the embedded RAM unit. The multiple processor integrated circuit can further include an input output unit coupled to the bus to provide input and output transactions for the processor units. The bus is configured to provide split transactions for the processor units coupled to the bus, providing better bandwidth utilization of the bus. The bus can be configured to transfer an entire cache line for the cache units of the processor units in a single clock cycle, wherein the bus is 256 bits wide.

Abstract: Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.

Abstract: A method and apparatus for making flow information available for binary manipulation tasks are disclosed. Flow information is generated and saved either by a compiler or by a flow information generator. A compiler generates the flow information directly from a source file while the compiler is compiling the source file into an executable file. A flow information generator generates the flow information from an executable file in a manner similar to a compiler. Further, the flow information generator groups the executable file into units of text and traces the units to produce the flow information. The binary information thus retrieved is saved and embedded either in a text or a header of the executable file or placed in a file separate from the executable file. The flow information may be used in binary manipulations including binary translations, binary-to-binary optimizations, program tracing, and program debugging.