Patents by Inventor Stephen Earl Seitsinger

Stephen Earl Seitsinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory architecture and systems and methods using the same
    Patent number: 6418063
    Abstract: A memory architecture 400 includes an array of memory cells partitioned into a plurality of subarrays 401. Each subarray 401 includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline 407 and each column associated with a pair of conductive half-bitlines 403. The first sense amplifier 402 is selectively coupled to selected pair of half-bitlines 403. A second sense amplifier 402 is selectively coupled to the selected pair of half-bitlines 403. A first local I/O line 404 is coupled to first sense amplifier 402 and a second local I/O line 404 is coupled to the second sense amplifier 402. First and second sets of global I/O lines 405 are selectively coupled to the first and second I/O lines 404.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: July 9, 2002
    Assignee: Silicon Aquarius, Inc.
    Inventors: Stephen Earl Seitsinger, Wayland Bart Holland
  • Memory architecture and systems and methods using the same
    Patent number: 5940329
    Abstract: A memory architecture 400 includes an array of memory cells partitioned into a plurality of subarrays 401. Each subarray 401 includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline 407 and each column associated with a pair of conductive half-bitlines 403. The first sense amplifier 402 is selectively coupled to selected pair of half-bitlines 403. A second sense amplifier 402 is selectively coupled to the selected pair of half-bitlines 403. A first local I/O line 404 is coupled to first sense amplifier 402 and a second local I/O line 404 is coupled to the second sense amplifier 402. First and second sets of global I/O lines 405 are selectively coupled to the first and second I/O lines 404.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: August 17, 1999
    Assignees: Silicon Aquarius, Inc., Silicon SA
    Inventors: Stephen Earl Seitsinger, Wayland Bart Holland