Patents by Inventor Stephen Edward Liles

Stephen Edward Liles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12057159
    Abstract: Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: August 6, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pramod Kolar, Stephen Edward Liles, Gregory Christopher Burda
  • Patent number: 11699483
    Abstract: Memory systems with burst mode having logic gates as sense elements and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first wordline, a second set of memory cells coupled to a second wordline, and a plurality of sense elements, not including any sense amplifiers. The control unit is configured to generate control signals for: in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first wordline coupled to each of a plurality of first set of bitlines, and (2) asserting a second wordline signal on the second wordline coupled to each of a plurality of second set of bitlines, and as part of a burst, outputting data corresponding to a subset of each of the first set of memory cells and the second set of memory cells.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: July 11, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pramod Kolar, Stephen Edward Liles, Gregory Christopher Burda
  • Patent number: 11587610
    Abstract: Memory systems having flying bitlines for improved burst mode read operations and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline. The memory system includes a control unit configured to generate control signals for simultaneously: asserting a first wordline signal on the first inner wordline coupled to each of a plurality of inner bitlines, and asserting a second wordline signal on the first outer wordline coupled to each of a plurality of outer bitlines, where each of the plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline, and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 21, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pramod Kolar, Stephen Edward Liles
  • Patent number: 9911472
    Abstract: Systems and methods are directed to managing signals in a dual voltage domain comprising a high voltage domain and a low voltage domain. A write bitline driver circuit receives complementary global write bitline signals as input signals from a global write bitline driver in the low voltage domain, and a write enable signal as an input signal in the high voltage domain. The write bitline driver circuit generates complementary local write bitline signals as output signals in the high voltage domain for activating bitlines of a memory bank in the high voltage domain. The complementary local write bitline signals are based on the complementary global write bitline signals, voltage level shifted from the low voltage domain to the high voltage domain and gated by the write enable signal.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 6, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Manish Garg
  • Patent number: 9768779
    Abstract: Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 19, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Krishnakumar Nadkarni, Stephen Edward Liles, Manish Garg
  • Patent number: 9640250
    Abstract: Systems and methods relate to memory operations in a memory array. A compare operation is performed using a sense amplifier. True and complement versions of a search bit are compared with true and complement versions of a data bit stored in a data row of the memory array to generate true and complement sense amplifier inputs. The true and complement sense amplifier inputs are amplified in the sense amplifier to generate a single-ended match signal. The single-ended match signal can be aggregated with other single-ended match signals in the data row to determine whether there is a hit or miss for a compare operation on the entire data row.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: May 2, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: David Paul Hoff, Stephen Edward Liles, Brian Joy Reed
  • Patent number: 9608637
    Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: March 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles, Chintan Hemendrakumar Shah
  • Publication number: 20170047930
    Abstract: Dynamic voltage level shifters employing pulse generation circuits are disclosed. In one aspect, a dynamic voltage level shifter includes a dynamic voltage level shifting circuit. The dynamic voltage level shifting circuit includes a pre-charge circuit configured to provide supply voltage of a first voltage domain to a dynamic node in response to a clock signal having pre-charge voltage. An evaluate circuit is configured to provide ground voltage to the dynamic node in response to an input signal having an active voltage while the clock signal has evaluate voltage. A keeper circuit is configured to provide a reduced drive strength to the dynamic node in response to pulse signal. The pulse signal is generated by a pulse generation circuit, wherein a pulse width of the pulse signal correlates to a difference in supply voltages of first and second voltage domains.
    Type: Application
    Filed: August 14, 2015
    Publication date: February 16, 2017
    Inventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles, Chintan Hemendrakumar Shah
  • Patent number: 9548089
    Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 17, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Stephen Edward Liles, Satendra Kumar Maurya, Kunal Garg, Chiaming Chai, Chintan Shah
  • Publication number: 20160359487
    Abstract: Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 8, 2016
    Inventors: Rahul Krishnakumar Nadkarni, Stephen Edward Liles, Manish Garg
  • Patent number: 9442675
    Abstract: Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: September 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles
  • Patent number: 9378789
    Abstract: Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 28, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: David Paul Hoff, Amey Kulkarni, Jason Philip Martzloff, Stephen Edward Liles
  • Patent number: 9019752
    Abstract: Static random access memory (SRAM) global bitline circuits for reducing glitches during read accesses, and related methods and systems are disclosed. A global bitline scheme in SRAM can reduce output load, reducing power consumption. In certain embodiments, SRAM includes an SRAM array. The SRAM includes a global bitline circuit for each SRAM array column. Each global bitline circuit includes memory access circuit that pre-charges local bitlines corresponding to bitcells in SRAM array. The data read from selected bitcell is read from its local bitline onto aggregated read bitline, an aggregation of local bitlines. The SRAM includes bitline evaluation circuit that sends data from aggregated read bitline onto global bitline. Instead of sending data based on rising transition of clock trigger, data is sent onto the global bitline based on falling transition of clock trigger. A global bitline scheme can be employed that reduces glitches and resulting increases in power consumption.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: April 28, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Joshua Lance Puckett, Stephen Edward Liles, Jason Philip Martzloff
  • Patent number: 9007817
    Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: April 14, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles, Kunal Garg
  • Publication number: 20140328113
    Abstract: Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.
    Type: Application
    Filed: October 9, 2013
    Publication date: November 6, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Chiaming Chai, Shaoping Ge, Stephen Edward Liles, Kunal Garg
  • Patent number: 8638153
    Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 28, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
  • Publication number: 20130257498
    Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Lam V. Nguyen, Jeffrey Herbert Fischer
  • Patent number: 8456929
    Abstract: Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: June 4, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Stephen Edward Liles, Chiaming Chai, Lakshmikant Mamileti
  • Publication number: 20110249518
    Abstract: Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.
    Type: Application
    Filed: April 7, 2010
    Publication date: October 13, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Stephen Edward Liles, Chiaming Chai, Lakshmikant Mamileti
  • Patent number: 7876631
    Abstract: Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: January 25, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Chiaming Chai, Stephen Edward Liles