Patents by Inventor Stephen Ellinwood Luce
Stephen Ellinwood Luce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8471306Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: July 28, 2011Date of Patent: June 25, 2013Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8421126Abstract: Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: June 20, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8236683Abstract: A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture.Type: GrantFiled: January 28, 2011Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Jeffrey Peter Gambino, Stephen Ellinwood Luce
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Publication number: 20110302542Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: July 28, 2011Publication date: December 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20110241082Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8026606Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.Type: GrantFiled: August 25, 2009Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Patent number: 8013342Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: November 14, 2007Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 8004289Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.Type: GrantFiled: August 26, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Thomas Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Stephen Ellinwood Luce, Edmund Juris Sprogis
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Patent number: 7989312Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: November 5, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20110136339Abstract: A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture.Type: ApplicationFiled: January 28, 2011Publication date: June 9, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey Peter Gambino, Stephen Ellinwood Luce
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Patent number: 7884475Abstract: A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture.Type: GrantFiled: October 16, 2007Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Jeffrey Peter Gambino, Stephen Ellinwood Luce
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Patent number: 7670927Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: GrantFiled: May 16, 2006Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20100044759Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: November 5, 2009Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry Bernstein, Timothy Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20090309223Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.Type: ApplicationFiled: August 25, 2009Publication date: December 17, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Patent number: 7585758Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.Type: GrantFiled: November 6, 2006Date of Patent: September 8, 2009Assignee: International Business Machines CorporationInventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper
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Publication number: 20090121260Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: November 14, 2007Publication date: May 14, 2009Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20090096102Abstract: A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture.Type: ApplicationFiled: October 16, 2007Publication date: April 16, 2009Applicant: International Business Machines CorporationInventors: Jeffrey Peter Gambino, Stephen Ellinwood Luce
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Patent number: 7474104Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.Type: GrantFiled: November 8, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Thomas Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffee, Stephen Ellinwood Luce, Edmund Juris Sprogis
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Publication number: 20080308948Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.Type: ApplicationFiled: August 26, 2008Publication date: December 18, 2008Inventors: Thomas Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Stephen Ellinwood Luce, Edmund Juris Sprogis
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Publication number: 20080105977Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.Type: ApplicationFiled: November 6, 2006Publication date: May 8, 2008Inventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper