Abstract: A printed circuit board having a substrate layer, at least one electrically conductive trace disposed on the substrate layer, and a solder mask layer disposed over the substrate layer and the electrically conductive trace, wherein the solder mask later includes a void region over at least a portion of the electrically conductive trace. Also, a method of optimizing printed circuit board designing including selecting printed circuit board data comprising at least a solder mask layer area, varying the solder mask layer area, determining an insertion loss value for each varied solder mask layer area, comparing the insertion loss values for each varied solder mask layer area, and selecting a solder mask layer area based on the comparing.

Abstract: A printed circuit board having a substrate layer, at least one electrically conductive trace disposed on the substrate layer, and a solder mask layer disposed over the substrate layer and the electrically conductive trace, wherein the solder mask later includes a void region over at least a portion of the electrically conductive trace. Also, a method of optimizing printed circuit board designing including selecting printed circuit board data comprising at least a solder mask layer area, varying the solder mask layer area, determining an insertion loss value for each varied solder mask layer area, comparing the insertion loss values for each varied solder mask layer area, and selecting a solder mask layer area based on the comparing.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

Abstract: A memory module connector (100) is described herein. The memory module connector (100) comprises a plurality of connector pins (102) distributed into a plurality of columns (104). The plurality of connector pins (102) further comprises a plurality of ground pins (106) for providing electrical ground to the memory module connector (100) and a plurality of signal pins (108) for carrying data signals across the memory module connector (100). Further, for each signal pin (108) provided in a column (104), each connector pin (102) adjacent to the signal pin (108) in an adjacent column (104) is a ground pin (106).

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: A memory module connector (100) is described herein. The memory module connector (100) comprises a plurality of connector pins (102) distributed into a plurality of columns (104). The plurality of connector pins (102) further comprises a plurality of ground pins (106) for providing electrical ground to the memory module connector (100) and a plurality of signal pins (108) for carrying data signals across the memory module connector (100). Further, for each signal pin (108) provided in a column (104), each connector pin (102) adjacent to the signal pin (108) in an adjacent column (104) is a ground pin (106).

Abstract: A system can include a memory circuit having a first signal via, a first signal return via, and at least one second signal return via located closer to the control signal via than the first signal return via.

Abstract: A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

Abstract: A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

Abstract: A first signal passes through a first layer of a circuit apparatus at a first propagation speed, and a second signal passes through a second layer of the circuit apparatus at a second propagation speed different from the first propagation speed.

Abstract: A computer system with various component modules with each of the modules interconnected with a single midplane board, thereby eliminating the need for ribbon cables to interconnect between the modules. One of the modules includes an embedded controller and associated data bus. An in-line connector is coupled in the data bus which receives either a jumper connector or interconnect connector. The interconnect connector intercepts the data bus from the embedded controller and transfers connection to a user added controller. The interconnect connector can operate in two modes, a single mode and a differential mode. The interconnect connector includes logic circuitry that determines the type of controller connected and places the interconnect connector in the appropriate mode. If the logic circuitry detects that a single-ended controller is connected to the interconnect connector, a quick switch, which is connected to one wire of the data bus, is closed, thereby grounding the one wire.

Abstract: A computer system with various component modules with each of the modules interconnected with a single midplane board, thereby eliminating the need for ribbon cables to interconnect between the modules. One of the modules includes an embedded controller and associated data bus. An in-line connector is coupled in the data bus which receives either a jumper connector or interconnect connector. The interconnect connector intercepts the data bus from the embedded controller and transfers connection to a user added controller. The interconnect connector can operate in two modes, a single mode and a differential mode The interconnect connector includes logic circuitry that determines the type of controller connected and places the interconnect connector in the appropriate mode. If the logic circuitry detects that a single-ended controller is connected to the interconnect connector, a quick switch, which is connected to one wire of the data bus, is closed, thereby grounding the one wire.

Abstract: A computer system with various component modules with each of the modules interconnected with a single midplane board, thereby eliminating the need for ribbon cables to interconnect between the modules. One of the modules includes an embedded controller and associated data bus. An in-line connector is coupled in the data bus which receives either a jumper connector or interconnect connector. The interconnect connector intercepts the data bus from the embedded controller and transfers connection to a user added controller. The interconnect connector can operate in two modes, a single mode and a differential mode. The interconnect connector includes logic circuitry that determines the type of controller connected and places the interconnect connector in the appropriate mode. If the logic circuitry detects that a single-ended controller is connected to the interconnect connector, a quick switch, which is connected to one wire of the data bus, is closed, thereby grounding the one wire.

Abstract: A bus configuration and associated termination for an Intel Slot 2 bus supporting communication for at least one Intel Pentium II Xeon processor. The Intel Slot 2 bus is configured in an in-line topology and includes a plurality of Intel Slot 2 bus connectors connected to the Intel Slot 2. A first plurality of bus terminators are electrically connected to a first end of the in-line Intel Slot 2 bus and a second plurality of bus terminators are electrically connected to a second end of the in-line Intel Slot 2 bus. The first and second plurality of bus terminators are constructed in accordance with termination specifications required by Intel on terminator cards which are inserted into unpopulated Intel Slot 2 bus connectors except that one end of the bus has the one hundred and fifty ohm pull-up resistor required by Intel replaced with an eighty two ohm pull-up resistor.